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最新推荐文章于 2024-05-20 13:50:31 发布

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最新推荐文章于 2024-05-20 13:50:31 发布

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分类专栏： TI芯片文章标签：内核 linux

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jacinto 内核驱动 – 4

3.2.2.10. PCIe端点
介绍
集成在Jacinto 7中的PCIe控制器IPs能够在根复杂模式(主机)或端点模式(设备)下运行。当在End Point (EP)模式下操作时，控制器可以配置为根据用例使用的任何功能(’ Test endpoint ‘和’ NTB '是目前Linux内核中唯一支持的PCIe EP功能)。
框图
以下是端点模式框架框图:
在这里插入图片描述

Features of J7ES
J7ES的特点
PCIe子系统有四个实例。以下是一些主要功能：
•每个实例都可以配置为在根复杂模式或端点模式下运行
•单通道或双通道配置，最高支持8.0 Gbps/通道（Gen3）
•端点（EP）模式下的单根I/O虚拟化
•6个物理功能(PF)
•16个虚拟功能（PF0、PF1、PF2和PF3各4个VF；PF4和PF5各0个VF）
•支持传统、MSI和MSI-X中断
•出站地址转换单元中可以有32种不同的地址映射。映射可以来自为每个PCIe实例保留的区域。
•例如PCIE0和PCIE1，SoC内存映射中有两个区域：
•128 MB区域，低32位地址
•地址高于32位的4 GB区域
•例如PCIE2和PCIE3，SoC内存映射中有两个区域：
•128 MB区域，地址高于32位
•地址高于32位的4 GB区域
J721E EVM的能力
EVM上有三个PCIe子系统实例。以下是每个实例的一些详细信息：

Instance	Supported lanes	Supported Connector
PCIE0	1 lane	Standard female connector
PCIE1	2 lane	Standard female connector
PCIE2	2 lane	m.2 connector keyed for SSD (M key)

硬件设置详细信息
默认情况下，J721E打算在根复杂模式下运行。因此，为了连接两个电路板，需要下面这样的专用电缆.

此电缆可从Adex Electronics (https://www.adexelec.com)获得.
修改电缆以移除CK+和CK-中的电阻器，以避免接地回路（电源）和冒烟的时钟驱动器（clk+/-）。
移除RST电阻以避免复位（PERST）从根复合体传播到端点。同样在根复合体到端点的环回连接中，运行Linux的端点应该在根复合体出现之前初始化。将重设从根复数传播到端点将导致端点的PORZ，这是应该避免的。
修改后的电缆末端应如下所示：
•A side

• B side

下面是两个背靠背连接的J721E EVM的图像。对于电缆的哪一端应连接到主机和设备没有限制.

对于端点模式，PCIE_1L_MODE_SEL(开关5)和PCIE_2L_MODE_SEL(开关6)应该设置为 ‘1’.

EP (End Point)设备配置
DTS修改
默认的dts被配置为在根复杂模式下使用。为了在端点模式中使用它，必须在dts文件中进行以下更改。
要在EP模式下配置J721E EVM测试版，请应用以下补丁:

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
index 57d72aa945b7..3384dd6063c2 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
@@ -734,7 +734,7 @@
};

&pcie0 {
-       pci-mode = <PCI_MODE_RC>;
+       pci-mode = <PCI_MODE_EP>;
        num-lanes = <1>;
};

@@ -754,6 +754,11 @@
        phy-names = "pcie_phy";
};

+&pcie0_ep {
+       phys = <&serdes0_pcie_link>;
+       phy-names = "pcie_phy";
+};
+
&pcie1_rc {
        reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
        phys = <&serdes1_pcie_link>;

要在EP模式下配置Alpha J721E EVM，请应用以下补丁:

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-proc-board-tps65917.dts b/arch/arm64/boot/dts/ti/k3-j721e-proc-board-tps65917.dts
index b9fece8d267c..d50f764c6642 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-proc-board-tps65917.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-proc-board-tps65917.dts
@@ -769,7 +769,7 @@
};

&pcie0 {
-       pci-mode = <PCI_MODE_RC>;
+       pci-mode = <PCI_MODE_EP>;
        num-lanes = <1>;
};

@@ -789,6 +789,11 @@
        phy-names = "pcie_phy";
};

+&pcie0_ep {
+       phys = <&serdes0_pcie_link>;
+       phy-names = "pcie_phy";
+};
+
&pcie1_rc {
        reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
        phys = <&serdes1_pcie_link>;

Linux驱动程序配置
必须启用以下配置选项才能将PCI控制器配置为用作“端点测试”功能驱动程序。

CONFIG_PCI_ENDPOINT=y
CONFIG_PCI_ENDPOINT_CONFIGFS=y
CONFIG_PCI_EPF_TEST=y
CONFIG_PCI_J721E=y
CONFIG_PCIE_CADENCE_EP=y

端点控制器设备和功能驱动程序
要查找系统中端点控制器设备的列表，请执行以下操作:

root@j7-evm:~# ls /sys/class/pci_epc/
d000000.pcie-ep

要查找系统中端点函数驱动程序的列表，请执行以下操作:

root@j7-evm:~# ls /sys/bus/pci-epf/drivers
pci_epf_test  pci_epf_ntb

使用pci-epf-test函数驱动程序
pci-epf-test函数驱动程序可以用来测试PCI控制器的端点功能。目前支持的一些测试包括:
Test Description

BAR	从 BAR一个已知的模式被写入和读取回来
Interrupt (legacy/MSI/MSI-X)	从EP触发一个Interrupt(legacy/MSI/MSI-X)
Read	从RC的缓冲区中读取数据，并对该数据执行循环冗余检查(CRC)
Write	将数据以RC格式写入缓冲区，并对该数据执行循环冗余检查(CRC)
Copy	数据从一个RC缓冲区拷贝到另一个RC缓冲区，并对该数据执行循环冗余检查(CRC)

在这里插入图片描述

创建pci-epf-test设备
可以使用配置文件创建PCI端点功能设备。创建pci-epf-test功能可以使用以下命令:

mount -t configfs none /sys/kernel/config
cd /sys/kernel/config/pci_ep/
mkdir functions/pci_epf_test/func1

以上命令创建了pci-epf-test功能设备。
PCI端点框架用可配置字段填充目录。.

root@j7-evm:/sys/kernel/config/pci_ep# ls functions/pci_epf_test/func1
baseclass_code  cache_line_size  deviceid  interrupt_pin  msi_interrupts  msix_interrupts  progif_code  revid  subclass_code  subsys_id  subsys_vendor_id  vendorid

当设备绑定到驱动程序时，驱动程序用默认值填充这些条目。pci-epf-test驱动程序用0xffff填充vendorid，用0x0001填充interrupt_pin.
r

oot@j7-evm:/sys/kernel/config/pci_ep# cat functions/pci_epf_test/func1/vendorid
0xffff
root@j7-evm:/sys/kernel/config/pci_ep# cat functions/pci_epf_test/func1/interrupt_pin
0x0001

配置pci-epf-test设备
用户可以通过配置文件对pci-epf-test设备进行配置。为了改变功能设备使用的vendorid和MSI中断的数量，可以使用以下命令:

root@j7-evm:/sys/kernel/config/pci_ep# echo 0x104c > functions/pci_epf_test/func1/vendorid

上面的命令将Texas Instruments配置为供应商.

root@j7-evm:/sys/kernel/config/pci_ep# echo 0xb00d > functions/pci_epf_test/func1/deviceid

上面的命令配置deviceid.

root@j7-evm:/sys/kernel/config/pci_ep# echo 2 > functions/pci_epf_test/func1/msi_interrupts
root@j7-evm:/sys/kernel/config/pci_ep# echo 2 > functions/pci_epf_test/func1/msix_interrupts

上面的命令配置中断的数量。2为正在配置的MSI和MSI-X中断数。MSI配置的中断数为1 ~ 32, MSI-X配置的中断数为1 ~ 2048。
pci-epf-test设备与EP控制器绑定
为了使端点功能设备有用，必须将它绑定到一个PCI端点控制器驱动程序。使用configfs将功能设备绑定到系统中存在的控制器驱动程序之一。

root@j7-evm:/sys/kernel/config/pci_ep# ln -s functions/pci_epf_test/func1 controllers/d000000.pcie-ep/

启动EP设备
为了让EP设备准备好建立链接，应该给出以下命令:

root@j7-evm:/sys/kernel/config/pci_ep# echo 1 > controllers/d000000.pcie-ep/start

当使用6个物理功能时，完整的序列如下所示:

mount -t configfs none /sys/kernel/config
cd /sys/kernel/config/pci_ep/
mkdir functions/pci_epf_test/func1
echo 0x104c > functions/pci_epf_test/func1/vendorid
echo 0xb00d > functions/pci_epf_test/func1/deviceid
echo 2 > functions/pci_epf_test/func1/msi_interrupts
echo 2 > functions/pci_epf_test/func1/msix_interrupts
ln -s functions/pci_epf_test/func1 controllers/d000000.pcie-ep/

mkdir functions/pci_epf_test/func2
echo 0x104c > functions/pci_epf_test/func2/vendorid
echo 0xb00d > functions/pci_epf_test/func2/deviceid
echo 2 > functions/pci_epf_test/func2/msi_interrupts
echo 2 > functions/pci_epf_test/func2/msix_interrupts
ln -s functions/pci_epf_test/func2 controllers/d000000.pcie-ep/

mkdir functions/pci_epf_test/func3
echo 0x104c > functions/pci_epf_test/func3/vendorid
echo 0xb00d > functions/pci_epf_test/func3/deviceid
echo 2 > functions/pci_epf_test/func3/msi_interrupts
echo 2 > functions/pci_epf_test/func3/msix_interrupts
ln -s functions/pci_epf_test/func3 controllers/d000000.pcie-ep/

mkdir functions/pci_epf_test/func4
echo 0x104c > functions/pci_epf_test/func4/vendorid
echo 0xb00d > functions/pci_epf_test/func4/deviceid
echo 2 > functions/pci_epf_test/func4/msi_interrupts
echo 2 > functions/pci_epf_test/func4/msix_interrupts
ln -s functions/pci_epf_test/func4 controllers/d000000.pcie-ep/

mkdir functions/pci_epf_test/func5
echo 0x104c > functions/pci_epf_test/func5/vendorid
echo 0xb00d > functions/pci_epf_test/func5/deviceid
echo 2 > functions/pci_epf_test/func5/msi_interrupts
echo 2 > functions/pci_epf_test/func5/msix_interrupts
ln -s functions/pci_epf_test/func5 controllers/d000000.pcie-ep/

mkdir functions/pci_epf_test/func6
echo 0x104c > functions/pci_epf_test/func6/vendorid
echo 0xb00d > functions/pci_epf_test/func6/deviceid
echo 2 > functions/pci_epf_test/func6/msi_interrupts
echo 2 > functions/pci_epf_test/func6/msix_interrupts
ln -s functions/pci_epf_test/func6 controllers/d000000.pcie-ep/
echo 1 > controllers/d000000.pcie-ep/start

如果要使用虚拟功能，需要将其绑定到物理功能。物理功能需要绑定到控制器。
使用虚拟功能的命令序列示例如下:

mount -t configfs none /sys/kernel/config
cd /sys/kernel/config/pci_ep/
mkdir functions/pci_epf_test/vf1
echo 0x104c > functions/pci_epf_test/vf1/vendorid
echo 0xb00d > functions/pci_epf_test/vf1/deviceid
echo 4 > functions/pci_epf_test/vf1/msi_interrupts
echo 8 > functions/pci_epf_test/vf1/msix_interrupts

mkdir functions/pci_epf_test/vf2
echo 0x104c > functions/pci_epf_test/vf2/vendorid
echo 0xb00d > functions/pci_epf_test/vf2/deviceid
echo 4 > functions/pci_epf_test/vf2/msi_interrupts
echo 8 > functions/pci_epf_test/vf2/msix_interrupts

mkdir functions/pci_epf_test/pf1
echo 0x104c > functions/pci_epf_test/pf1/vendorid
echo 0xb00d > functions/pci_epf_test/pf1/deviceid
echo 16 > functions/pci_epf_test/pf1/msi_interrupts
echo 16 > functions/pci_epf_test/pf1/msix_interrupts

ln -s functions/pci_epf_test/vf1 functions/pci_epf_test/pf1
ln -s functions/pci_epf_test/vf2 functions/pci_epf_test/pf1
ln -s functions/pci_epf_test/pf1 controllers/d800000.pcie-ep

echo 1 > controllers/d800000.pcie-ep/start

主机设备配置
PCI EP设备必须在PCI主机设备之前接通电源并进行配置。此限制是因为PCI主机不支持热插拔。
Linux驱动程序配置
要使用“端点测试”PCI设备，必须启用以下配置选项。

CONFIG_PCI=y
CONFIG_PCI_ENDPOINT_TEST=y
CONFIG_PCIE_CADENCE_HOST=y
lspci output
0000:00:00.0 PCI bridge: Texas Instruments Device b00d
0000:01:00.0 Unassigned class [ff00]: Texas Instruments Device b00d
0000:01:00.1 Unassigned class [ff00]: Texas Instruments Device b00d
0000:01:00.2 Unassigned class [ff00]: Texas Instruments Device b00d
0000:01:00.3 Unassigned class [ff00]: Texas Instruments Device b00d
0000:01:00.4 Unassigned class [ff00]: Texas Instruments Device b00d
0000:01:00.5 Unassigned class [ff00]: Texas Instruments Device b00d
0001:00:00.0 PCI bridge: Texas Instruments Device b00d
0002:00:00.0 PCI bridge: Texas Instruments Device b00d

使用端点测试功能设备
pci_endpoint_test测试驱动程序创建端点测试功能设备，该设备将由以下pcitest实用程序使用。pci_endpoint_test可以内置到内核中，也可以作为模块构建。为了测试遗留中断，必须在主机中禁用MSI中断。
tools/pci/中添加的pcitest.sh可用于运行所有默认的pci端点测试。在使用pcitest.sh之前，pcitest.c应该按照以下步骤编译:

cd <kernel-dir>
make headers_install ARCH=arm64
aarch64-linux-gnu-gcc -Iusr/include tools/pci/pcitest.c -o pcitest
cp pcitest  <rootfs>/usr/sbin/
cp tools/pci/pcitest.sh <rootfs>

pcitest输出
pcitest的用法如下:

root@j7-evm:~# ./pcitest -h
usage:  -h                      Print this help message
[options]
Options:
        -D <dev>                PCI endpoint test device {default: /dev/pci-endpoint-test.0}
        -b <bar num>            BAR test (bar number between 0..5)
        -m <msi num>            MSI test (msi number between 1..32)
        -x <msix num>           MSI-X test (msix number between 1..2048)
        -i <irq type>           Set IRQ type (0 - Legacy, 1 - MSI, 2 - MSI-X)
        -e                      Clear IRQ
        -I                      Get current IRQ type configured
        -l                      Legacy IRQ test
        -r                      Read buffer test
        -w                      Write buffer test
        -c                      Copy buffer test
        -s <size>               Size of buffer {default: 100KB}
示例用法
root@j7-evm:~# ./pcitest -i 1 -D /dev/pci-endpoint-test.0
SET IRQ TYPE TO MSI:            OKAY
root@j7-evm:~# ./pcitest -m 1 -D /dev/pci-endpoint-test.0
MSI1:           OKAY
root@j7-evm:~# ./pcitest -e -D /dev/pci-endpoint-test.0
CLEAR IRQ:              OKAY
root@j7-evm:~# ./pcitest -i 2 -D /dev/pci-endpoint-test.0
SET IRQ TYPE TO MSI-X:          OKAY
root@j7-evm:~# ./pcitest -x 1 -D /dev/pci-endpoint-test.0
MSI-X1:         OKAY
root@j7-evm:~# ./pcitest -e -D /dev/pci-endpoint-test.0
CLEAR IRQ:              OKAY

脚本pcitest.sh公司运行所有条测试、中断测试、读取测试、写入测试和复制测试。
文件

Serial No	Location	Description
1	drivers/pci/endpoint/pci-epc-core.c	PCI Endpoint Framework
	drivers/pci/endpoint/pci-ep-cfs.c	
	drivers/pci/endpoint/pci-epc-mem.c	
	drivers/pci/endpoint/pci-epf-core.c	
2	drivers/pci/endpoint/functions/pci-epf-test.c	PCI Endpoint Function Driver
3	drivers/misc/pci_endpoint_test.c	PCI Driver
4	tools/pci/pcitest.c	PCI Userspace Tools
	tools/pci/pcitest.sh	
5	drivers/pci/controller/pci-j721e.c	PCI Controller Driver
	drivers/pci/controller/pcie-cadence.c	
	drivers/pci/controller/pcie-cadence-ep.c	
	drivers/pci/endpoint/pcie-cadence-host.c

3.2.2.11. PCIe背板
介绍
PCIe背板支持多个主机之间的RC端口通信和数据共享。
在这里插入图片描述

PCIe背板使用多功能端点控制器的多个实例实现。每个主机应连接到一个单独的端点控制器实例，并且每个主机将枚举另一个主机作为一个独立的函数。
PCIe使用NTB（非透明网桥）使两台主机相互通信。尽管J721E没有显式的NTB控制器，但可以使用多个端点控制器实例来实现NTB功能。对于PCIe背板（连接2个以上主机），可以使用多功能端点控制器的多个实例对NTB控制器的聚合进行建模。
在下图中，PCI NTB功能将SoC配置为具有多个PCIe端点（EP）实例，以便将来自一个EP控制器的事务路由到另一个EP控制器。一旦PCI NTB功能将SoC配置为多个EP实例，HOST1和HOST2就可以使用SoC作为网桥进行通信.

   +-------------+                                   +-------------+
   |             |                                   |             |
   |    HOST1    |                                   |    HOST2    |
   |             |                                   |             |
   +------^------+                                   +------^------+
          |                                                 |
          |                                                 |
+---------|-------------------------------------------------|---------+
|  +------v------+                                   +------v------+  |
|  |             |                                   |             |  |
|  |     EP      |                                   |     EP      |  |
|  | CONTROLLER1 |                                   | CONTROLLER2 |  |
|  |             <----------------------------------->             |  |
|  |             |                                   |             |  |
|  |             |                                   |             |  |
|  |             |  SoC With Multiple EP Instances   |             |  |
|  |             |  (Configured using NTB Function)  |             |  |
|  +-------------+                                   +-------------+  |
+---------------------------------------------------------------------+

NTB软件体系结构
下面给出了NTB在主机端和EP端的软件体系结构。上半部分是主机端NTB架构，下半部分是端点端NTB架构。
在这里插入图片描述

背板设置
下图显示了连接到两个DRA7 EVM的J721E EVM。这里，两块DRA7x板使用J721E作为背板相互通信.

背板配置
背板DTS覆盖文件
以下DTS覆盖文件在EP模式下配置PCIe控制器，还包含用于创建NTB功能设备的设备树节点:

arch/arm64/boot/dts/ti/k3-j721e-pcie-backplane.dtso

为了应用dts覆盖文件，在u-boot提示符中应该给出以下命令:

#setenv name_overlays k3-j721e-pcie-backplane.dtbo

EP侧配置(J721E背板)
J721E背板应该在任何主机启动之前启动。一旦内核出现提示符，应该给出以下命令来启动PCIe0和PCIe1的LTSSM:

cd /sys/kernel/config/pci_ep/
echo 1 > controllers/d800000.pcie-ep/start
echo 1 > controllers/d000000.pcie-ep/start

（PCIe2也可以配置为NTB，但尚未测试）。
RC侧配置
需要相互通信的主机可以在EP启动后按任意顺序购买。主机启动后，必须在每个主机中执行以下步骤。
由于多个功能驱动程序（pci-endpoint-test and ntb_hw_epf）使用相同的供应商ID和设备ID，因此应首先从现有驱动程序对设备进行ubund。

echo 0000:01:00.0 > /sys/bus/pci/devices/0000\:01\:00.0/driver/unbind

从现有驱动程序解除绑定后，它应该绑定到ntb_hw_epf驱动程序.

echo 0000:01:00.0 > /sys/bus/pci/drivers/ntb_hw_epf/bind

然后绑定一个NTB应用程序驱动程序。这里，ntb_netdev必定会在PCIe上模拟以太网。这将为每个主机创建一个新的以太网接口。

modprobe ntb_transport
modprobe ntb_netdev
Kernel Configs
EP Side (J721E Backplane)
CONFIG_PCI_ENDPOINT=y
CONFIG_PCI_ENDPOINT_CONFIGFS=y
CONFIG_PCI_EPF_NTB=y
CONFIG_PCI_J721E=y
CONFIG_PCIE_CADENCE=y
CONFIG_PCIE_CADENCE_EP=y
Host Side
CONFIG_PCI=y
CONFIG_PCI_MSI=y
CONFIG_NTB=m
CONFIG_NTB_EPF=m
CONFIG_NTB_TRANSPORT=m
CONFIG_NTB_NETDEV=m
RC controller configs

额外的信息
如需更多资料，请参阅:

<Processor_SDK_install_dir>/board-support/linux-[ver]/Documentation/PCI/endpoint/pci-test-ntb.txt

3.2.2.12. PCIe根复合体
介绍
PCI Express（PCIe）模块是一种多通道I/O互连，提供低引脚计数、高可靠性和高速数据传输，每通道每方向传输速率高达8.0 Gbps。它是继ISA和PCI总线之后的第三代I/O互连技术，设计用于多个市场领域的通用串行I/O互连，包括台式机、移动设备、服务器、存储和嵌入式通信。
J7ES的特点
PCIe子系统有四个实例。以下是一些主要功能：
•每个实例都可以配置为在根复杂模式或端点模式下运行
•单通道或双通道配置，最高支持8.0 Gbps/通道（Gen3）
•支持传统、MSI和MSI-X中断
•出站地址转换单元中可以有32种不同的地址映射。映射可以来自为每个PCIe实例保留的区域。
•例如PCIE0和PCIE1，SoC内存映射中有两个区域：
•128 MB区域，低32位地址
•地址高于32位的4 GB区域
•例如PCIE2和PCIE3，SoC内存映射中有两个区域：
•128 MB区域，地址高于32位
•地址高于32位的4 GB区域
J721E EVM的能力
EVM上有三个PCIe子系统实例。以下是每个实例的一些详细信息:

Instance	Supported lanes	Supported Connector
PCIE0	1 lane	Standard female connector
PCIE1	2 lane	Standard female connector
PCIE2	2 lane	m.2 connector keyed for SSD (M key)

硬件设置详细信息
默认情况下，J721E打算在根复杂模式下运行。
对于端点模式，PCIE_1L_MODE_SEL（开关5）和PCIE_2L_MODE_SEL（开关6）应设置为“0”。

RC软件体系结构
以下是根复杂模式的软件体系结构:
在这里插入图片描述

以下是图中各层的简要说明:
•有不同的驱动程序用于连接的PCIe设备，如pci_endpoint_test, tg-3, r8169, xhci-pci, ahci等。它可以是特定于供应商的，如大多数以太网卡(tg3、r8169)，也可以是特定于类的，如xhci-pci和ahci。这些驱动程序中的每一个都将与它自己的特定于领域的堆栈交互。例如，tg3将与网络堆栈接口，xhci-pci将与USB堆栈接口。
•PCI核心层扫描PCIe总线来识别和检测任何PCIe设备。它还基于vendorid、deviceid和class为PCIe设备绑定上一层的驱动程序。
•PCI BIOS层处理资源管理。例如，为BARs分配内存资源。
•最底层由PCIe平台驱动程序组成，如pcie-cadence, pcie-designware等。pci-j721e和pci-dra7xx是TI在这些驱动程序上的包装器。它们配置特定于平台的控制器并执行实际的寄存器写入。
RC设备配置
DTS修改
默认dts配置为在根复杂模式下使用。
Linux驱动程序配置
必须启用以下配置选项才能将PCI控制器配置为在根复杂模式下使用.

CONFIG_SOCIONEXT_SYNQUACER_PREITS=y
CONFIG_PCI=y
CONFIG_PCI_MSI=y
CONFIG_PCI_J721E=y
CONFIG_PCIE_CADENCE=y
CONFIG_PCIE_CADENCE_HOST=y

测试细节
RC应该枚举任何off-the-shelf的PCIe卡。它已经过以太网卡、NVMe卡、PCIe USB卡、PCIe WiFi卡、PCIe SATA卡以及环回模式下的J721E测试。
为了查看是否检测到连接的卡，应使用lspci实用程序。根据卡的不同，可以使用不同的实用程序。
以下是其中一些的输出：
•环回模式（J721E EVM到J721E EVM）
通过遵循PCIe端点文档中端点（EP）的端点（EP）设备配置部分和根复合体（RC）的主机设备配置部分中说明的步骤，可以在环回模式下连接两个J721E EVM。将使用这些步骤为端点（EP）配置pci epf测试驱动程序。
根复合体（RC）设备上的lspci输出如下:

root@j7-evm:~# lspci
0000:00:00.0 PCI bridge: Texas Instruments Device b00d
0000:01:00.0 Unassigned class [ff00]: Texas Instruments Device b00d
0000:01:00.1 Unassigned class [ff00]: Texas Instruments Device b00d
0000:01:00.2 Unassigned class [ff00]: Texas Instruments Device b00d
0000:01:00.3 Unassigned class [ff00]: Texas Instruments Device b00d
0000:01:00.4 Unassigned class [ff00]: Texas Instruments Device b00d
0000:01:00.5 Unassigned class [ff00]: Texas Instruments Device b00d
0001:00:00.0 PCI bridge: Texas Instruments Device b00d
0002:00:00.0 PCI bridge: Texas Instruments Device b00d

•WiFi卡
•lspci输出

root@j7-evm:~# lspci
0000:00:00.0 PCI bridge: Texas Instruments Device b00d
0000:01:00.0 Network controller: Intel Corporation Wireless 3160 (rev 6b)
0001:00:00.0 PCI bridge: Texas Instruments Device b00d
0002:00:00.0 PCI bridge: Texas Instruments Device b00d

•使用ping进行测试

root@j7-evm:~# ping 192.168.10.1 -w 10|
PING 192.168.10.1 (192.168.10.1): 56 data bytes
64 bytes from 192.168.10.1: seq=0 ttl=64 time=176.985 ms
64 bytes from 192.168.10.1: seq=1 ttl=64 time=49.840 ms
64 bytes from 192.168.10.1: seq=2 ttl=64 time=32.125 ms
64 bytes from 192.168.10.1: seq=3 ttl=64 time=4.652 ms
64 bytes from 192.168.10.1: seq=4 ttl=64 time=70.805 ms
64 bytes from 192.168.10.1: seq=6 ttl=64 time=195.564 ms
64 bytes from 192.168.10.1: seq=7 ttl=64 time=9.321 ms
64 bytes from 192.168.10.1: seq=8 ttl=64 time=5.784 ms
64 bytes from 192.168.10.1: seq=9 ttl=64 time=18.015 ms
•NVMe SSD

•lspci输出

root@j7-evm:~# lspci -vv
0000:00:00.0 PCI bridge: Texas Instruments Device b00d (prog-if 00 [Normal decode])
    Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
    Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
    Interrupt: pin A routed to IRQ 0
    Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
    I/O behind bridge: None
    Memory behind bridge: None
    Prefetchable memory behind bridge: None
    Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-
    BridgeCtl: Parity- SERR- NoISA- VGA- VGA16- MAbort- >Reset- FastB2B-
        PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
    Capabilities: [80] Power Management version 3
        Flags: PMEClk- DSI- D1+ D2- AuxCurrent=0mA PME(D0+,D1+,D2-,D3hot+,D3cold-)
        Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
    Capabilities: [90] MSI: Enable- Count=1/1 Maskable+ 64bit+
        Address: 0000000000000000  Data: 0000
        Masking: 00000000  Pending: 00000000
    Capabilities: [b0] MSI-X: Enable- Count=1 Masked-
        Vector table: BAR=0 offset=00000000
        PBA: BAR=0 offset=00000008
    Capabilities: [c0] Express (v2) Root Port (Slot+), MSI 00
        DevCap:     MaxPayload 256 bytes, PhantFunc 0
            ExtTag- RBE+
        DevCtl:     CorrErr- NonFatalErr- FatalErr- UnsupReq-
            RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+
            MaxPayload 128 bytes, MaxReadReq 512 bytes
        DevSta:     CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr- TransPend-
        LnkCap:     Port #0, Speed 8GT/s, Width x1, ASPM L1, Exit Latency L1 <8us
            ClockPM- Surprise- LLActRep- BwNot+ ASPMOptComp+
        LnkCtl:     ASPM Disabled; RCB 64 bytes Disabled- CommClk-
            ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
        LnkSta:     Speed 2.5GT/s (downgraded), Width x2 (strange)
            TrErr- Train- SlotClk- DLActive- BWMgmt- ABWMgmt-
        SltCap:     AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise-
            Slot #0, PowerLimit 0.000W; Interlock- NoCompl-
        SltCtl:     Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg-
            Control: AttnInd Off, PwrInd Off, Power+ Interlock-
        SltSta:     Status: AttnBtn- PowerFlt- MRL+ CmdCplt- PresDet- Interlock-
            Changed: MRL- PresDet- LinkState-
        RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible-
        RootCap: CRSVisible-
        RootSta: PME ReqID 0000, PMEStatus- PMEPending-
        DevCap2: Completion Timeout: Range B, TimeoutDis+, LTR+, OBFF Not Supported ARIFwd+
            AtomicOpsCap: Routing- 32bit- 64bit- 128bitCAS-
        DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled ARIFwd-
            AtomicOpsCtl: ReqEn- EgressBlck-
        LnkCtl2: Target Link Speed: 8GT/s, EnterCompliance- SpeedDis-
            Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
            Compliance De-emphasis: -6dB
        LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-, EqualizationPhase1-
            EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
    Capabilities: [100 v2] Advanced Error Reporting
        UESta:      DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
        UEMsk:      DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
        UESvrt:     DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
        CESta:      RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr-
        CEMsk:      RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+
        AERCap:     First Error Pointer: 00, ECRCGenCap+ ECRCGenEn- ECRCChkCap+ ECRCChkEn-
            MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap-
        HeaderLog: 00000000 00000000 00000000 00000000
        RootCmd: CERptEn- NFERptEn- FERptEn-
        RootSta: CERcvd- MultCERcvd- UERcvd- MultUERcvd-
            FirstFatal- NonFatalMsg- FatalMsg- IntMsg 0
        ErrorSrc: ERR_COR: 0000 ERR_FATAL/NONFATAL: 0000
    Capabilities: [150 v1] Device Serial Number 00-00-00-00-00-00-00-00
    Capabilities: [300 v1] Secondary PCI Express <?>
    Capabilities: [4c0 v1] Virtual Channel
        Caps:       LPEVC=0 RefClk=100ns PATEntryBits=1
        Arb:        Fixed- WRR32- WRR64- WRR128-
        Ctrl:       ArbSelect=Fixed
        Status:     InProgress-
        VC0:        Caps:   PATOffset=00 MaxTimeSlots=1 RejSnoopTrans-
            Arb:    Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256-
            Ctrl:   Enable+ ID=0 ArbSelect=Fixed TC/VC=ff
            Status: NegoPending- InProgress-
        VC1:        Caps:   PATOffset=00 MaxTimeSlots=1 RejSnoopTrans-
            Arb:    Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256-
            Ctrl:   Enable- ID=1 ArbSelect=Fixed TC/VC=00
            Status: NegoPending- InProgress-
        VC2:        Caps:   PATOffset=00 MaxTimeSlots=1 RejSnoopTrans-
            Arb:    Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256-
            Ctrl:   Enable- ID=2 ArbSelect=Fixed TC/VC=00
            Status: NegoPending- InProgress-
        VC3:        Caps:   PATOffset=00 MaxTimeSlots=1 RejSnoopTrans-
            Arb:    Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256-
            Ctrl:   Enable- ID=3 ArbSelect=Fixed TC/VC=00
            Status: NegoPending- InProgress-
    Capabilities: [5c0 v1] Address Translation Service (ATS)
        ATSCap:     Invalidate Queue Depth: 01
        ATSCtl:     Enable-, Smallest Translation Unit: 00
    Capabilities: [640 v1] Page Request Interface (PRI)
        PRICtl: Enable- Reset-
        PRISta: RF- UPRGI- Stopped+
        Page Request Capacity: 00000001, Page Request Allocation: 00000000
    Capabilities: [900 v1] L1 PM Substates
        L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+
            PortCommonModeRestoreTime=255us PortTPowerOnTime=26us
        L1SubCtl1: PCI-PM_L1.2- PCI-PM_L1.1- ASPM_L1.2- ASPM_L1.1-
            T_CommonMode=0us LTR1.2_Threshold=0ns
        L1SubCtl2: T_PwrOn=10us
    Kernel modules: pci_endpoint_test, ntb_hw_epf

0001:00:00.0 PCI bridge: Texas Instruments Device b00d (prog-if 00 [Normal decode])
    Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
    Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
    Latency: 0
    Interrupt: pin A routed to IRQ 0
    Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
    I/O behind bridge: None
    Memory behind bridge: 18100000-181fffff [size=1M]
    Prefetchable memory behind bridge: None
    Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-
    BridgeCtl: Parity- SERR- NoISA- VGA- VGA16- MAbort- >Reset- FastB2B-
        PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
    Capabilities: [80] Power Management version 3
        Flags: PMEClk- DSI- D1+ D2- AuxCurrent=0mA PME(D0+,D1+,D2-,D3hot+,D3cold-)
        Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
    Capabilities: [90] MSI: Enable- Count=1/1 Maskable+ 64bit+
        Address: 0000000000000000  Data: 0000
        Masking: 00000000  Pending: 00000000
    Capabilities: [b0] MSI-X: Enable- Count=1 Masked-
        Vector table: BAR=0 offset=00000000
        PBA: BAR=0 offset=00000008
    Capabilities: [c0] Express (v2) Root Port (Slot+), MSI 00
        DevCap:     MaxPayload 256 bytes, PhantFunc 0
            ExtTag- RBE+
        DevCtl:     CorrErr- NonFatalErr- FatalErr- UnsupReq-
            RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+
            MaxPayload 128 bytes, MaxReadReq 512 bytes
        DevSta:     CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr- TransPend-
        LnkCap:     Port #0, Speed 8GT/s, Width x2, ASPM L1, Exit Latency L1 <8us
            ClockPM- Surprise- LLActRep- BwNot+ ASPMOptComp+
        LnkCtl:     ASPM Disabled; RCB 64 bytes Disabled- CommClk-
            ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
        LnkSta:     Speed 8GT/s (ok), Width x2 (ok)
            TrErr- Train- SlotClk- DLActive- BWMgmt- ABWMgmt+
        SltCap:     AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise-
            Slot #0, PowerLimit 0.000W; Interlock- NoCompl-
        SltCtl:     Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg-
            Control: AttnInd Off, PwrInd Off, Power+ Interlock-
        SltSta:     Status: AttnBtn- PowerFlt- MRL+ CmdCplt- PresDet- Interlock-
            Changed: MRL- PresDet- LinkState-
        RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible-
        RootCap: CRSVisible-
        RootSta: PME ReqID 0000, PMEStatus- PMEPending-
        DevCap2: Completion Timeout: Range B, TimeoutDis+, LTR+, OBFF Not Supported ARIFwd+
            AtomicOpsCap: Routing- 32bit- 64bit- 128bitCAS-
        DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled ARIFwd+
            AtomicOpsCtl: ReqEn- EgressBlck-
        LnkCtl2: Target Link Speed: 8GT/s, EnterCompliance- SpeedDis-
            Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
            Compliance De-emphasis: -6dB
        LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete+, EqualizationPhase1+
            EqualizationPhase2+, EqualizationPhase3+, LinkEqualizationRequest-
    Capabilities: [100 v2] Advanced Error Reporting
        UESta:      DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
        UEMsk:      DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
        UESvrt:     DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
        CESta:      RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr-
        CEMsk:      RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+
        AERCap:     First Error Pointer: 00, ECRCGenCap+ ECRCGenEn- ECRCChkCap+ ECRCChkEn-
            MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap-
        HeaderLog: 00000000 00000000 00000000 00000000
        RootCmd: CERptEn- NFERptEn- FERptEn-
        RootSta: CERcvd- MultCERcvd- UERcvd- MultUERcvd-
            FirstFatal- NonFatalMsg- FatalMsg- IntMsg 0
        ErrorSrc: ERR_COR: 0000 ERR_FATAL/NONFATAL: 0000
    Capabilities: [150 v1] Device Serial Number 00-00-00-00-00-00-00-00
    Capabilities: [300 v1] Secondary PCI Express <?>
    Capabilities: [4c0 v1] Virtual Channel
        Caps:       LPEVC=0 RefClk=100ns PATEntryBits=1
        Arb:        Fixed- WRR32- WRR64- WRR128-
        Ctrl:       ArbSelect=Fixed
        Status:     InProgress-
        VC0:        Caps:   PATOffset=00 MaxTimeSlots=1 RejSnoopTrans-
            Arb:    Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256-
            Ctrl:   Enable+ ID=0 ArbSelect=Fixed TC/VC=ff
            Status: NegoPending- InProgress-
        VC1:        Caps:   PATOffset=00 MaxTimeSlots=1 RejSnoopTrans-
            Arb:    Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256-
            Ctrl:   Enable- ID=1 ArbSelect=Fixed TC/VC=00
            Status: NegoPending- InProgress-
        VC2:        Caps:   PATOffset=00 MaxTimeSlots=1 RejSnoopTrans-
            Arb:    Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256-
            Ctrl:   Enable- ID=2 ArbSelect=Fixed TC/VC=00
            Status: NegoPending- InProgress-
        VC3:        Caps:   PATOffset=00 MaxTimeSlots=1 RejSnoopTrans-
            Arb:    Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256-
            Ctrl:   Enable- ID=3 ArbSelect=Fixed TC/VC=00
            Status: NegoPending- InProgress-
    Capabilities: [5c0 v1] Address Translation Service (ATS)
        ATSCap:     Invalidate Queue Depth: 01
        ATSCtl:     Enable-, Smallest Translation Unit: 00
    Capabilities: [640 v1] Page Request Interface (PRI)
        PRICtl: Enable- Reset-
        PRISta: RF- UPRGI- Stopped+
        Page Request Capacity: 00000001, Page Request Allocation: 00000000
    Capabilities: [900 v1] L1 PM Substates
        L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+
            PortCommonModeRestoreTime=255us PortTPowerOnTime=26us
        L1SubCtl1: PCI-PM_L1.2- PCI-PM_L1.1- ASPM_L1.2- ASPM_L1.1-
            T_CommonMode=0us LTR1.2_Threshold=0ns
        L1SubCtl2: T_PwrOn=10us
    Kernel modules: pci_endpoint_test, ntb_hw_epf

0001:01:00.0 Non-Volatile memory controller: Lite-On Technology Corporation M8Pe Series NVMe SSD (rev 01) (prog-if 02 [NVM Express])
    Subsystem: Marvell Technology Group Ltd. M8Pe Series NVMe SSD
    Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
    Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
    Latency: 0
    Interrupt: pin A routed to IRQ 0
    Region 0: Memory at 18120000 (64-bit, non-prefetchable) [size=16K]
    Expansion ROM at 18100000 [size=128K]
    Capabilities: [40] Power Management version 3
        Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
        Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
    Capabilities: [50] MSI: Enable- Count=1/1 Maskable+ 64bit+
        Address: 0000000000000000  Data: 0000
        Masking: 00000000  Pending: 00000000
    Capabilities: [70] Express (v2) Endpoint, MSI 00
        DevCap:     MaxPayload 128 bytes, PhantFunc 0, Latency L0s unlimited, L1 unlimited
            ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset+ SlotPowerLimit 0.000W
        DevCtl:     CorrErr- NonFatalErr- FatalErr- UnsupReq-
            RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop- FLReset-
            MaxPayload 128 bytes, MaxReadReq 512 bytes
        DevSta:     CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr- TransPend-
        LnkCap:     Port #0, Speed 8GT/s, Width x4, ASPM L1, Exit Latency L1 <64us
            ClockPM+ Surprise- LLActRep- BwNot- ASPMOptComp+
        LnkCtl:     ASPM Disabled; RCB 64 bytes Disabled- CommClk-
            ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
        LnkSta:     Speed 8GT/s (ok), Width x2 (downgraded)
            TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
        DevCap2: Completion Timeout: Not Supported, TimeoutDis+, LTR+, OBFF Via message
            AtomicOpsCap: 32bit- 64bit- 128bitCAS-
        DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled
            AtomicOpsCtl: ReqEn-
        LnkCtl2: Target Link Speed: 8GT/s, EnterCompliance- SpeedDis-
            Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
            Compliance De-emphasis: -6dB
        LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete+, EqualizationPhase1+
            EqualizationPhase2+, EqualizationPhase3+, LinkEqualizationRequest-
    Capabilities: [b0] MSI-X: Enable+ Count=19 Masked-
        Vector table: BAR=0 offset=00002000
        PBA: BAR=0 offset=00003000
    Capabilities: [100 v2] Advanced Error Reporting
        UESta:      DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
        UEMsk:      DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
        UESvrt:     DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
        CESta:      RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr-
        CEMsk:      RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+
        AERCap:     First Error Pointer: 00, ECRCGenCap+ ECRCGenEn+ ECRCChkCap+ ECRCChkEn+
            MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap-
        HeaderLog: 00000000 00000000 00000000 00000000
    Capabilities: [148 v1] Device Serial Number 00-00-00-00-00-00-00-00
    Capabilities: [158 v1] Power Budgeting <?>
    Capabilities: [168 v1] Alternative Routing-ID Interpretation (ARI)
        ARICap:     MFVC- ACS-, Next Function: 0
        ARICtl:     MFVC- ACS-, Function Group: 0
    Capabilities: [178 v1] Secondary PCI Express <?>
    Capabilities: [2b8 v1] Latency Tolerance Reporting
        Max snoop latency: 0ns
        Max no snoop latency: 0ns
    Capabilities: [2c0 v1] L1 PM Substates
        L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+
            PortCommonModeRestoreTime=10us PortTPowerOnTime=10us
        L1SubCtl1: PCI-PM_L1.2- PCI-PM_L1.1- ASPM_L1.2- ASPM_L1.1-
            T_CommonMode=0us LTR1.2_Threshold=0ns
        L1SubCtl2: T_PwrOn=10us
    Kernel driver in use: nvme
    Kernel modules: nvme

0002:00:00.0 PCI bridge: Texas Instruments Device b00d (prog-if 00 [Normal decode])
    Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
    Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
    Interrupt: pin A routed to IRQ 0
    Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
    I/O behind bridge: None
    Memory behind bridge: None
    Prefetchable memory behind bridge: None
    Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-
    BridgeCtl: Parity- SERR- NoISA- VGA- VGA16- MAbort- >Reset- FastB2B-
        PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
    Capabilities: [80] Power Management version 3
        Flags: PMEClk- DSI- D1+ D2- AuxCurrent=0mA PME(D0+,D1+,D2-,D3hot+,D3cold-)
        Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
    Capabilities: [90] MSI: Enable- Count=1/1 Maskable+ 64bit+
        Address: 0000000000000000  Data: 0000
        Masking: 00000000  Pending: 00000000
    Capabilities: [b0] MSI-X: Enable- Count=1 Masked-
        Vector table: BAR=0 offset=00000000
        PBA: BAR=0 offset=00000008
    Capabilities: [c0] Express (v2) Root Port (Slot+), MSI 00
        DevCap:     MaxPayload 256 bytes, PhantFunc 0
            ExtTag- RBE+
        DevCtl:     CorrErr- NonFatalErr- FatalErr- UnsupReq-
            RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+
            MaxPayload 128 bytes, MaxReadReq 512 bytes
        DevSta:     CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr- TransPend-
        LnkCap:     Port #0, Speed 8GT/s, Width x2, ASPM L1, Exit Latency L1 <8us
            ClockPM- Surprise- LLActRep- BwNot+ ASPMOptComp+
        LnkCtl:     ASPM Disabled; RCB 64 bytes Disabled- CommClk-
            ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
        LnkSta:     Speed 2.5GT/s (downgraded), Width x2 (ok)
            TrErr- Train- SlotClk- DLActive- BWMgmt- ABWMgmt-
        SltCap:     AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise-
            Slot #0, PowerLimit 0.000W; Interlock- NoCompl-
        SltCtl:     Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg-
            Control: AttnInd Off, PwrInd Off, Power+ Interlock-
        SltSta:     Status: AttnBtn- PowerFlt- MRL+ CmdCplt- PresDet- Interlock-
            Changed: MRL- PresDet- LinkState-
        RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible-
        RootCap: CRSVisible-
        RootSta: PME ReqID 0000, PMEStatus- PMEPending-
        DevCap2: Completion Timeout: Range B, TimeoutDis+, LTR+, OBFF Not Supported ARIFwd+
            AtomicOpsCap: Routing- 32bit- 64bit- 128bitCAS-
        DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled ARIFwd-
            AtomicOpsCtl: ReqEn- EgressBlck-
        LnkCtl2: Target Link Speed: 8GT/s, EnterCompliance- SpeedDis-
            Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
            Compliance De-emphasis: -6dB
        LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-, EqualizationPhase1-
            EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
    Capabilities: [100 v2] Advanced Error Reporting
        UESta:      DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
        UEMsk:      DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
        UESvrt:     DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
        CESta:      RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr-
        CEMsk:      RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+
        AERCap:     First Error Pointer: 00, ECRCGenCap+ ECRCGenEn- ECRCChkCap+ ECRCChkEn-
            MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap-
        HeaderLog: 00000000 00000000 00000000 00000000
        RootCmd: CERptEn- NFERptEn- FERptEn-
        RootSta: CERcvd- MultCERcvd- UERcvd- MultUERcvd-
            FirstFatal- NonFatalMsg- FatalMsg- IntMsg 0
        ErrorSrc: ERR_COR: 0000 ERR_FATAL/NONFATAL: 0000
    Capabilities: [150 v1] Device Serial Number 00-00-00-00-00-00-00-00
    Capabilities: [300 v1] Secondary PCI Express <?>
    Capabilities: [4c0 v1] Virtual Channel
        Caps:       LPEVC=0 RefClk=100ns PATEntryBits=1
        Arb:        Fixed- WRR32- WRR64- WRR128-
        Ctrl:       ArbSelect=Fixed
        Status:     InProgress-
        VC0:        Caps:   PATOffset=00 MaxTimeSlots=1 RejSnoopTrans-
            Arb:    Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256-
            Ctrl:   Enable+ ID=0 ArbSelect=Fixed TC/VC=ff
            Status: NegoPending- InProgress-
        VC1:        Caps:   PATOffset=00 MaxTimeSlots=1 RejSnoopTrans-
            Arb:    Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256-
            Ctrl:   Enable- ID=1 ArbSelect=Fixed TC/VC=00
            Status: NegoPending- InProgress-
        VC2:        Caps:   PATOffset=00 MaxTimeSlots=1 RejSnoopTrans-
            Arb:    Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256-
            Ctrl:   Enable- ID=2 ArbSelect=Fixed TC/VC=00
            Status: NegoPending- InProgress-
        VC3:        Caps:   PATOffset=00 MaxTimeSlots=1 RejSnoopTrans-
            Arb:    Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256-
            Ctrl:   Enable- ID=3 ArbSelect=Fixed TC/VC=00
            Status: NegoPending- InProgress-
    Capabilities: [5c0 v1] Address Translation Service (ATS)
        ATSCap:     Invalidate Queue Depth: 01
        ATSCtl:     Enable-, Smallest Translation Unit: 00
    Capabilities: [640 v1] Page Request Interface (PRI)
        PRICtl: Enable- Reset-
        PRISta: RF- UPRGI- Stopped+
        Page Request Capacity: 00000001, Page Request Allocation: 00000000
    Capabilities: [900 v1] L1 PM Substates
        L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+
            PortCommonModeRestoreTime=255us PortTPowerOnTime=26us
        L1SubCtl1: PCI-PM_L1.2- PCI-PM_L1.1- ASPM_L1.2- ASPM_L1.1-
            T_CommonMode=0us LTR1.2_Threshold=0ns
        L1SubCtl2: T_PwrOn=10us
    Kernel modules: pci_endpoint_test, ntb_hw_epf

•使用hdparm进行测试

root@j7-evm:~# hdparm -tT /dev/nvme0n1

/dev/nvme0n1:
Timing cached reads: 3678 MB in 2.00 seconds = 1840.32 MB/sec
Timing buffered disk reads: 2252 MB in 3.00 seconds = 750.34 MB/sec

•使用dd进行测试

root@j7-evm:~# time dd if=/dev/urandom of=/home/root/srctest_file_pci_2199 bs=1M count=10|
10+0 records in
10+0 records out
real        0m 0.17s
user        0m 0.00s
sys     0m 0.08s

chocolate2018

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2021-02-22

jacinto 内核驱动 – 43.2.2.10. PCIe端点介绍集成在Jacinto 7中的PCIe控制器IPs能够在根复杂模式(主机)或端点模式(设备)下运行。当在End Point (EP)模式下操作时，控制器可以配置为根据用例使用的任何功能(’ Test endpoint ‘和’ NTB '是目前Linux内核中唯一支持的PCIe EP功能)。框图以下是端点模式框架框图:Features of J7ESJ7ES的特点PCIe子系统有四个实例。以下是一些主要功能：•每个实例都可以配
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