VCO的一些碎碎念

1. 为什么CM2次谐波相位对齐了反而相噪性能变差了？
   
   A: 可能跟其他因素有关，比如幅值。

2. 什么是ISF函数？是VCO的噪声传输函数吗？
   冲击灵敏度函数，可以看作传输函数的时域表达，意义是用来描述不同时刻噪声注入对VCO输出波形的相位影响。
   

3. VCO noise factor和其他RF模块noise factor之间的区别：归一化的参考标准不同
   
   Ref：E. Hegazi, H. Sjoland and A. A. Abidi, “A filtering technique to lower LC oscillator phase noise,” in IEEE Journal of Solid-State Circuits, vol. 36, no. 12, pp. 1921-1930, Dec. 2001, doi: 10.1109/4.972142

4. Current-limited regime是什么？
   如下所示的原理图，在输出幅度变化影响交叉耦合管、电流源工作状态时，带来的两种模式变化。
   当电流源偏置较小，振荡幅度在$(0,V_{DD})$之间时，电流源可以保持在饱和区恒定输出，交叉耦合管工作在开关模式，流过交叉耦合管的电流就像一个方波信号，经谐振网络滤除之后可输出正弦波。
   
   
   
   Ref: A. Hajimiri and T. H. Lee, “Design issues in CMOS differential LC oscillators,” in IEEE Journal of Solid-State Circuits, vol. 34, no. 5, pp. 717-724, May 1999, doi: 10.1109/4.760384.

5. voltage-limited regime是什么？
   如果4.中的尾电流源电流设置得很大，振荡幅度接近甚至超过$V_{DD}$时，由于波谷电压会迫使交叉耦合管源极电压降低，导致$M_{tail}$进入三极管区，电流效率下降。此时开始进入电压限制区，无法再通过增加$I_{bias}$进一步提高摆幅。

Note that (2) loses its validity as the amplitude approaches the supply voltage because both NMOS and PMOS pairs will enter the triode region at the peaks of the voltage. Also the tail NMOS transistor may spend most (or even all) of its time in the linear region. This behavior can be seen in the simulated voltages and currents shown in Fig. 3. The tank voltage will be clipped at by the PMOS transistors and at ground by the NMOS transistors. Therefore, for the oscillator of Fig. 1(a), the tank voltage amplitude does not significantly exceed Note that since the tail transistor is in the triode region, the tail current does not stay constant. Thus, the drain-source voltage of the differential NMOS transistors can drop significantly，resulting in a large drop in their drain current, as shown in Fig. 3. This region of operation is known as the voltage-limited regime.

当尾电流的偏置电流大到一定程度之后，从current-limited regime进入到voltage-limited regime。因此电流偏置VCO的尾电流存在一个最大值。

Ref: A. Hajimiri and T. H. Lee, “Design issues in CMOS differential LC oscillators,” in IEEE Journal of Solid-State Circuits, vol. 34, no. 5, pp. 717-724, May 1999, doi: 10.1109/4.760384.

6. 共模差模的电流流向
   
   ref：M. Shahmohammadi, M. Babaie and R. B. Staszewski, “A 1/f Noise Upconversion Reduction Technique for Voltage-Biased RF CMOS Oscillators,” in IEEE Journal of Solid-State Circuits, vol. 51, no. 11, pp. 2610-2624, Nov. 2016, doi: 10.1109/JSSC.2016.2602214.

因此，如果这时在交叉耦合管尾部加一个电感，会形成二次谐波的电流回路，恶化VCO的相位噪声。

ref: Y. Hu, T. Siriburanon and R. B. Staszewski, “A Low-Flicker-Noise 30-GHz Class-F23 Oscillator in 28-nm CMOS Using Implicit Resonance and Explicit Common-Mode Return Path,” in IEEE Journal of Solid-State Circuits, vol. 53, no. 7, pp. 1977-1987, July 2018, doi: 10.1109/JSSC.2018.2818681.

7. Groszkowski’s effect 是什么？

8. Class-F,B,C VCO输出信号形状比较
   
   
   ref: Babaie, Masoud; Staszewski, Robert Bogdan (2013) A Class-F CMOS Oscillator. In : IEEE Journal of Solid-State Circuits, vol. 48, n° 12, p. 3120–3133. DOI: 10.1109/JSSC.2013.2273823.

9. 电压偏置型B类VCO漏极电压流波形，以及电流谐波成分频谱图：
   由于交叉耦合管的非线性，电压偏置型VCO直接进入voltage-limited区域。
   

10. 电压偏置型D类VCO漏极电压流波形，以及电流谐波成分频谱图：
    由于交叉耦合管非线性的影响，经过谐振器电感的电流曲线不是光滑的，存在由于晶体管工作区转变引起的小突起。相比于B类VCO，D类VCO的漏极电流谐波成分更低。
    
    带有二次谐波的D类VCO的ISF波形图：
    
    ref: Shahmohammadi, Mina; Babaie, Masoud; Staszewski, Robert Bogdan (2016) A 1/f Noise Upconversion Reduction Technique for Voltage-Biased RF CMOS Oscillators. In : IEEE Journal of Solid-State Circuits, vol. 51, n° 11, p. 2610–2624. DOI: 10.1109/JSSC.2016.2602214.

11. 为什么VCO中的交叉耦合管更常用NMOS管而不是PMOS管？
    我比较认同下面这个答案：（源于http://bbs.eetop.cn/thread-622661-1-1.html）
    

12. 什么是frequency pulling？什么是frequency pushing?
    Here term frequency pushing refers to a change in VCO frequency due to a change in the power supply voltage. Typical value for one of the minicircuit VCO device is 0.30 MHz/V.
    Here term frequency pulling refers to a change in VCO frequency due to a change in the load on the VCO output. Typical value for one of the minicircuit VCO device is 0.80 (MHz) peak-to-peak at 12dBr.