ppi 数据集_8255 PPI的数据流程图(可编程外围接口)

ppi 数据集

Data flow diagram | 8255 PPI


Image Source: https://2.bp.blogspot.com/-OqH_QF6yswE/WBZDgM7Y3lI/AAAAAAAAAhA/fGZWez7kHTMJJN-NunwBRs_McNnjvPWiQCLcB/s1600/8255.png

图片来源:https://2.bp.blogspot.com/-OqH_QF6yswE/WBZDgM7Y3lI/AAAAAAAAAhA/fGZWez7kHTMJJN-NunwBRs_McNnjvPWiQCLcB/s1600/8255.png

The data flow diagram of the 8255 PPI given above shows the internal working of the IC hoe data is transferred within it and what pins perform these functions. It is further explained as follows:

上面给出的8255 PPI数据流程图显示了IC hoe数据的内部工作在其中传输,以及哪些引脚执行这些功能。 进一步解释如下:

Internal Bus

内部总线

Here, you can see that we have 8 bit of internal bus for the 8255 PPI. Therefore, only 8 bits of data can be transferred between the 8255 IC and the interfaced device at a time.

在这里,您可以看到8255 PPI有8位内部总线。 因此,一次只能在8255 IC和接口设备之间传输8位数据。

Data Bus Buffer

数据总线缓冲器

The data bus buffer performs the transfer of 8 bits of data from the 8255 PPI to the microprocessor or other devices it is interfaced with.

数据总线缓冲区将8位数据从8255 PPI传输到与其连接的微处理器或其他设备。

Power Supply

电源供应

Here, we have 1 pin for +5V of power supply and 1 pin for ground voltage.

在这里,我们有1个用于+ 5V电源的引脚和1个用于接地电压的引脚。

Read- Write Control Logic

读写控制逻辑

As the name suggests, the Read Write control logic is responsible for all the read-write operations happening in any of the ports. It is controlled by the following pins:

顾名思义,读写控制逻辑负责任何端口中发生的所有读写操作。 它由以下引脚控制:

  • RD': For reading data, it should be reset.

    RD' :要读取数据,应将其重置。

  • WR': For writing data, it should be reset.

    WR' :要写入数据,应将其重置。

  • A0 and A1: These two pins together decide which port or control word will be selected for data transferring purpose.

    A0和A1 :这两个引脚共同决定为数据传输选择哪个端口或控制字。

  • RESET: It sets all the pin to their default values.

    复位 :将所有引脚设置为其默认值。

  • CS': For chip selection.

    CS' :用于芯片选择。

Group A control

A组对照

This unit controls the ports that fall under group A, i.e. Port A and Port C- upper.

本机控制属于组A的端口,即端口A和端口C-上。

Group B control

B组控制

This unit controls the ports that fall under group B, i.e. Port B and Port C- lower.

本机控制属于组B的端口,即端口B和端口C-low。

Group A- Port A

组A-端口A

It is the port A which contains its 8-bit data lines for I/O purpose, and it is controlled by the Group A control.

端口A包含用于I / O的8位数据线,并由A组控件控制。

Group A- Port C upper

A组-C口上部

It contains the higher 4-bit data lines of port C. It is also controlled by the Group A control since it falls in group A category. 

它包含端口C的较高4位数据线。由于它属于A组类别,因此它也由A组控件控制。

Group B- Port B

B组-B端口

It is the port B which contains its 8-bit data lines for I/O purpose, and it is controlled by the Group B control.

端口B包含用于I / O的8位数据线,并由组B控件控制。

Group A- Port C upper

A组-C口上部

It is the lower half of the Port C, i.e. it contains the lower 4-bit data lines of port C. It is also controlled by the Group B control. 

它是端口C的下半部分,即它包含端口C的低4位数据线。它也由组B控件控制。

翻译自: https://www.includehelp.com/embedded-system/data-flow-diagram-of-8255-ppi-programmable-peripheral-interface.aspx

ppi 数据集

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