半加法器和全加法器_半加法，全加法的设计以及使用半加法制作全加法

半加法器和全加法器

半加法器 (Half Adder)

The logic circuit which performs the addition of 2 bits is called Half- Adder. It is a kind of combinational circuit. It contains two binary inputs "augend" and "addend" and two binary outputs Sum and Carry.

执行2位加法的逻辑电路称为Half-Adder。 它是一种组合电路。 它包含两个二进制输入“ augend”和“ addend”以及两个二进制输出Sum和Carry 。

The Sum bit (S) and the Carry bit (C) are given according to the rules of Binary Addition which can be summarized in the form of truth table as,

求和位( S )和进位位( C )是根据二进制加法规则给出的，可以用真值表的形式总结为：

A	B	Sum (S)	Carry (C)
0	0	0	0
0	1	1	0
1	0	1	0
1	1	0	1

一个	乙	总和(S)	携带(C)
0	0	0	0
0	1个	1个	0
1个	0	1个	0
1个	1个	0	1个

K-Map Simplification

K图简化

We use K-Map to obtain the expression for Sum and Carry bit which is as,

我们使用K-Map获得Sum and Carry位的表达式，即

Upon obtaining the Boolean expressions, we can observe that Boolean Expression for Sum is nothing but the Exclusive OR function for two inputs and the Boolean Expression for carrying is the same as AND function. Thus, the circuit diagram for Half Adder can be drawn using an XOR gate and AND gate as shown in the above image.

在获得布尔表达式后，我们可以观察到Sum的布尔表达式只不过是两个输入的异或函数，而用于携带的布尔表达式与AND函数相同。 因此，如上图所示，可以使用异或门和与门绘制半加器的电路图。

完全加法器 (Full Adder)

Full Adder is an arithmetic circuit which performs the arithmetic sum of 3-input bits. It consists of 3 inputs and 2 outputs. One additional input is the Carry bit (C) in which represents the carry from the previous significant position.

Full Adder是一种算术电路，用于执行3输入位的算术和。 它由3个输入和2个输出组成。 一个附加输入是进位位( C )，其中表示前一个有效位置的进位。

Similarly, as in Half-Adder, we have two outputs Sum (S) and Carry (C), which can be obtained using the rules of Binary Addition and can be summarized in a Truth Table as,

同样，在Half-Adder中，我们有两个输出Sum( S )和Carry( C )，可以使用二进制加法规则获得它们，并可以在Truth Table中汇总为：

A	B	C	Sum (S)	Carry (C)
0	0	0	0	0
0	0	1	1	0
0	1	0	1	0
0	1	1	0	1
1	0	0	1	0
1	0	1	0	1
1	1	0	0	1
1	1	1	1	1

一个	乙	C	总和(S)	携带(C)
0	0	0	0	0
0	0	1个	1个	0
0	1个	0	1个	0
0	1个	1个	0	1个
1个	0	0	1个	0
1个	0	1个	0	1个
1个	1个	0	0	1个
1个	1个	1个	1个	1个

K-Map Simplification

K图简化

We use K-Map to obtain the expression for Sum and Carry bit which is as,

我们使用K-Map获得Sum and Carry位的表达式，即

The logic circuit for Full Adder can be drawn as,

全加法器的逻辑电路可以画为：

使用半加器的全加器 (Full Adder using Half Adder)

A Full Adder can also be implemented using two half adders and one OR gate.

完全加法器也可以使用两个半加法器和一个或门来实现。

The circuit diagram for this can be drawn as,

电路图可以绘制为

And, it could be represented in block diagram as,

而且，它可以在框图中表示为

The Boolean expression for Sum and Carry is as,

Sum and Carry的布尔表达式为，

    Sum     = A ⊕ B ⊕ C
    Carry   = AB + (A ⊕ B). C
            = AB + ( A. B + A. B). C
            = AB + A. BC + A. B. C
            = B (A + A. C) + A. B. C
            = B [(A+ A) (A + C)] + A. B. C
            = AB + AC + A. B. C
            = AB + C (B + A. B)
            = AB + C [(B + A) (B + B)]
            = AB + BC + AC

翻译自: https://www.includehelp.com/basics/designing-of-half-adder-full-adder-and-making-full-adder-using-half-adder.aspx

半加法器和全加法器