以半加器实现全加器

module fulladder(	input wire in_1,
						input wire in_2,
						input wire cin,   //进位
						
						output wire sum,
						output wire count
    );
wire hfsum1;
wire hfcount1;
wire hfcount2;
halfadder  halfadder_inst1
(    						.in_1(in_1),
							.in_2(in_2),
							.sum(hfsum1),
							.count(hfcount1)
    );
halfadder  halfadder_inst2
(    						.in_1(cin),
							.in_2(hfsum1),
							.sum(sum),
							.count(hfcount2)
    );
assign count = hfcount1 | hfcount2;  //或运算

endmodule

半加器：

module halfadder(    input wire in_1,
							input wire in_2,
							output wire sum,
							output wire count
    );
assign {count,sum} = in_1+in_2;


endmodule

module vtf_fulladder;

	// Inputs
	reg in_1;
	reg in_2;
	reg cin;

	// Outputs
	wire sum;
	wire count;

	// Instantiate the Unit Under Test (UUT)
	fulladder uut (
		.in_1(in_1), 
		.in_2(in_2), 
		.cin(cin), 
		.sum(sum), 
		.count(count)
	);

	initial begin
		// Initialize Inputs
		in_1 = 0;
		in_2 = 0;
		cin = 0;

		// Wait 100 ns for global reset to finish
		#100;

        
		// Add stimulus here

	end
	
		always #10 in_1<= {$random} %2;  //取随机数对2求余（0或者1） 
		always #10 in_2<= {$random} %2;
		always #10 cin <= {$random} %2;
      
endmodule