If an implementation includes the Multiprocessing Extensions, translation table walks must access da
ta or unified
caches, or data and unified caches, of other agents participating in the coherency protocol, according to the
shareability attributes described in the TTBR. These shareability attributes must be consistent with the shareability
attributes for the translation tables themselves.
IRGN, bits[6, 0], in an implementation that includes the Multiprocessing Extensions Inner region bits. Indicates the Inner Cacheability attributes for the memory associated with the
translation table walks. The pos sible values of IRGN[1:0] are:
0b00 Normal memory, Inner Non-cacheable.
0b01 Normal memory, Inner Write-Back Write-Allocate Cacheable.
0b10 Normal memory, Inner Write-Through Cacheable.
0b11 Normal memory, Inner Write-Back no Write-Allocate Cacheable.
The attributes should match, not just be similar.
Also the Cortex-A9 only supports WB/WA. From memory WB/nWA will get treated as WB/WA. Any WT regions get treated as non-cacheable.
[0] | IRGN[1] | Indicates inner cacheability for the translation table walk: IRGN[1], IRGN[0] 00 = Non-cacheable 01 = Write-Back Write-Allocate 10 = Write-Through, no allocate on write 11 = Write-Back no allocate on write. Page table walks do look-ups in the da |