有一点需要注意,下面以一个状态机为例进行说明。
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
entity statem is port (
clk : in std_logic;
rst : in std_logic;
selin : in std_logic;
num : out std_logic_vector (1 downto 0)
); end statem;
architecture alg of statem is
Type mystate is (st0,st1,st2,st3);
signal current_state,next_state : mystate;
begin
sync:process(clk,rst)
begin
if (rst = '1')then
current_state <= st0;
elsif (clk'event and clk = '1')then
current_state <= next_state;
end if;
end process sync;
nex:pro