library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity taxi is
port(clk:in std_logic;
start:in std_logic;
wait_signal:in std_logic;
mile:in std_logic;
one_way:in std_logic;
rst:in std_logic;
cost0,cost1,cost2,cost3:out std_logic_vector(3 downto 0);
min0,min1:out std_logic_vector(3 downto 0);
km0,km1:out std_logic_vector(3 downto 0));
end;
architecture bhv of taxi is
signal mile_r1,mile_r2,mile_clk,start_r,clk1hz:std_logic;
signal count:integer range 0 to 29;
signal sec:integer range 0 to 59;
signal c0,c1,c2,c3:std_logic_vector(3 downto 0);
signal k0,k1,m0,m1:std_logic_vector(3 downto 0);
signal en0,en1:std_logic;
signal wait_clk,cost_clk:std_logic;
begin
U1:process( rst,clk) -- 分频
begin
if rst='0' then
if clk'event and clk='1' then
if count=31 then
count<=0;clk1hz<=
EDA课设-基于VHDL的简易出租车计价器设计
最新推荐文章于 2024-09-09 10:00:14 发布
本文介绍了使用VHDL进行电子设计自动化(EDA)课程设计的一个项目——简易出租车计价器的详细设计过程。内容可能较旧,请注意时效性。
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