MSP432笔记--序

     之前总念叨着,TI大法好,于是在学C51的同时,开始研究TI的低功耗单片机MSP430,从G2到F6系列,做过一些简单的项目,完成实验室的一些基本要求还是绰绰有余。半年之后,也就是15年前半年,TI出了其32位超低功耗单片机MSP432,官网上说LAUNCHPAD是限量版的黑色,于是便和队友下了订单,两天后,从德州寄到大连。

然后虽然是东西到手了,但是丝毫没有时间和精力去学,因为考试周+暑期的电赛培训占去了大部分时间,于是一直吃灰到去年年底。

    某天心血来潮,把板子连上电脑,按照官方的文档配置IAR环境,写下第一个432程序

1 #include "msp432p401r"
2 
3 int main()
4 {   
5         return 0;
6 }

     对,就是这么简单粗暴,只加了一个头文件,直接编译,烧写。主要是测试配置环境的步骤有没有出错,之后可以写一下IAR新建工程的配置过程,相比较IAR for msp430 ,ARM版的IAR,配置过程略微复杂,需要指定头文件位置。

   毁掉了开箱程序后,实现了一下blink,然后继续吃土到前几天。

   因为项目的需求和重新燃起的兴趣,又开始研究MSP432,找了一些为数不多的资料,意识到不能再用之前配置寄存器的编程方法继续进行,大量的寄存器和繁琐的配置使得新手不容易入门,习惯于430编程的虽可以较好的直接移植,但总觉得固件库编程更是一种趋势,于是放弃之前的思路,着手从库函数入手研究,结合官方的文档以及其他网友的研究资料,加上自己的实践,把这一过程完整的记录下来,用来整理思路,加深印象,也方便与大家交流。

  

转载于:https://www.cnblogs.com/JZTD/p/5361066.html

MSP432 低功耗高性能并存10.1 Digital I/O Introduction The digital I/O features include: • Independently programmable individual I/Os • Any combination of input or output • Individually configurable interrupts for ports (available for certain ports only) • Independent input and output data registers • Individually configurable pullup or pulldown resistors • Wake-up capability from ultra-low power modes (available for certain ports only) • Individually configurable high drive I/Os (available for certain I/Os only) Devices within the family may have up to eleven digital I/O ports implemented (P1 to P10 and PJ). Most ports contain eight I/O lines; however, some ports may contain less (see the device-specific data sheet for ports available). Each I/O line is individually configurable for input or output direction, and each can be individually read or written. Each I/O line is individually configurable for pullup or pulldown resistors. Certain ports have interrupt and wake-up capability from ultra-low power modes (see device specific data sheet for ports with interrupt and wake-up capability). Each interrupt can be individually enabled and configured to provide an interrupt on a rising or falling edge of an input signal. All interrupts are fed into an encoded Interrupt Vector register, allowing the application to determine which sub-pin of a port has generated the event. Individual ports can be accessed as byte-wide ports or can be combined into half-word-wide ports. Port pairs P1 and P2, P3 and P4, P5 and P6, P7 and P8, and so on, are associated with the names PA, PB, PC, PD, and so on, respectively. All port registers are handled in this manner with this naming convention. The main exception are the interrupt vector registers, for example, interrupts for ports P1 and P2 must be handled through P1IV and P2IV, PAIV does not exist. When writing to port PA with half-word operations, all 16 bits are written to the port. When writing to the lower byte of port PA using byte operations, the upper byte remains unchanged. Similarly, writing to the upper byte of port PA using byte instructions leaves the lower byte unchanged. When writing to a port that contains less than the maximum number of bits possible, the unused bits are don't care. Ports PB, PC, PD, PE, and PF behave similarly.
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