SSD Arch

eaglelau

已于 2023-07-13 08:45:59 修改

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分类专栏： SSD NVMe 文章标签：数学建模

于 2023-06-27 11:35:24 首次发布

本文链接：https://blog.csdn.net/eaglelau/article/details/131412570

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文章探讨了固态硬盘(SSD)中的并行性层次，包括平面并行、通道并行和位向并行，这些机制提升了I/O性能并隐藏了闪存读写操作的延迟。同时，文章也讨论了FTL（闪存转换层）在地址映射、磨损均衡和垃圾回收中的作用，以及通道数量和FTL对SSD功耗的影响。

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Analytical Model of SSD Parallelism

An SSD is a complex device consisting of flash chips, micro-controller, e.g., ARM, memory, which is DRAM or SRAM, and host interface, e.g., SATA or PCIe. The software component of an SSD is called Flash Translation Layer (FTL). It is responsible for (i) translating a logical address into physical address, (ii) evenly distributing the wear-outs, and (iii) consolidating (recliaming) the invalid pages. In designing an SSD, it is very important that all design parameters, e.g., the number of channels, the number of ways, physical page size, address translation algorithms, garbage collection algorithms, wear leveling algorithms etc., are determined, properly incorporating the interactions among these components and the SSDs’ workload characteristics (or target usage).