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分类专栏： SSD NVMe 文章标签：数学建模

于 2023-06-27 11:35:24 首次发布

本文链接：https://blog.csdn.net/eaglelau/article/details/131412570

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文章探讨了固态硬盘(SSD)中的并行性层次，包括平面并行、通道并行和位向并行，这些机制提升了I/O性能并隐藏了闪存读写操作的延迟。同时，文章也讨论了FTL（闪存转换层）在地址映射、磨损均衡和垃圾回收中的作用，以及通道数量和FTL对SSD功耗的影响。

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Analytical Model of SSD Parallelism

An SSD is a complex device consisting of flash chips, micro-controller, e.g., ARM, memory, which is DRAM or SRAM, and host interface, e.g., SATA or PCIe. The software component of an SSD is called Flash Translation Layer (FTL). It is responsible for (i) translating a logical address into physical address, (ii) evenly distributing the wear-outs, and (iii) consolidating (recliaming) the invalid pages. In designing an SSD, it is very important that all design parameters, e.g., the number of channels, the number of ways, physical page size, address translation algorithms, garbage collection algorithms, wear leveling algorithms etc., are determined, properly incorporating the interactions among these components and the SSDs’ workload characteristics (or target usage).

An SSD consists of a number of physical components, e.g., NAND chips, bus, micro-controllers. These components work independently (or in a synchronized manner) which yields multiple concurrent activities in the device. A latency of an I/O request is governed by the concurrent processing of this I/O request among a number of SSD components.

SSDs exploit various levels of IO parallelism, such as plane parallelism, channel parallelism, and way parallelism, to boost up the I/O performance and to hide latency of flash write and read operations.

Plane Parallelism: The internal IO behavior of flash memory can be implemented in parallel by using multiple registers at the same time. Since the data transfer time between the flash controller and a register (82usec for Samsung NAND flash (Samsung, 2006)) is much shorter than the programming time of the flash page (900usec for Samsung NAND flash (Samsung, 2006)), the two-page programming operation can be conducted in parallel. This is called ‘plane parallelism’. Figure 3 shows the timing diagram of plane parallelism. Plane parallelism can also be used for read operations.

Channel Parallelism: Using several channels, the flash controller concurrently processes multiple IOs. This is called ‘channel parallelism’. Before the flash controller writes data to Flash 1, channel switching delay, denoted as Ch, occurs. Because channel switching delay is sufficiently short (33usec (Yoo et al., 2011)), the flash controller can write the pages to each flash memory at about the same time.

Way Parallelism: Flash memories in the same channel can process IOs in parallel. This is called ‘way parallelism’. In Figure 4(b), the flash controller can utilize way parallelism using Flash 0 and 2 in Channel 0. Because the flash memories share the same channel, a flash memory in the channel can transfer data with flash controller only if the channel is not occupied by another flash memory operation. Before the start of Page B operation, way switching delay(Way) occurs because Flash 0 and Flash 2 are connected to different ways. After way switching delay, the flash controller transfers Page B data to Flash 2 and then Flash 2 starts page write operation.

By using these kinds of IO parallel methods, SSDs achieve higher IO bandwidth.

We define the term IO latency as the time interval between the arrival of the IO command from the host to the device and the time when the I/O device sends the IO interrupt notifying the completion of an IO command. Terms used in each IO latency model are listed in Table 1.

Intel X-25M主流SSD规格：