地平线—征程2（Journey 2-J2）芯片详解（6）—PIN脚描述

写在前面

本系列文章主要讲解地平线征程2（Journey 2-J2）芯片的相关知识，希望能帮助更多的同学了解和认识征程2（Journey 2-J2）芯片。

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 错过其他章节的同学可以电梯直达目录↓↓↓

地平线—征程2（Journey 2-J2）芯片详解——目录-CSDN博客

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2. 硬件架构

2.3 PIN脚描述

此部分定义了信号的类型，如下表所示：

Abbreviation	Description
I	Digital input
O	Digital output
IO	Digital input/output, controlled by software or function module
AI	Analog input
AO	Analog output
AIO	Analog input/output
CIN	Crystal oscillator input
COUT	Crystal oscillator output
P	Power supply
G	Ground
PD	With internal pull-down resistor
PU	With internal pull-up resistor
S	With Schmitt trigger feature
R	With output slew rate control feature

2.3.1 电源引脚

J2的电源比较多，此部分主要描述了电源的类型、PIN脚位置和功能，如下表所示：

Pin Name	Number	Ball	Description
Digital Core Power
VDD_CORE_AO	2	M6, N6	Always On domain core power 0.9 V ± 10%
VDD_CORE_PD	4	H9, J9, K9, K11	Shutdown domain core power 0.9 V ± 10%
VDD_CPU	5	L8, L9 M8, N8, P8	Cortex A53 core power 1 GHz @0.9 V ± 10% 1.25 GHz @1.0 V + 5%,- 10%
VDD_DDR	6	H13, J13, K13 L13, M13, N13	DDR subsystem core power 2667 Mbps @1.0 V ± 5% 2133 Mbps @0.9 V ± 5%
VDD_CNN0	8	E11, E13 F11, F13 G11, G13 H11, J11	BPU0 core power 800 MHz @0.9 V ± 10% 850 MHz @1.0 V + 5%,- 10%
VDD_CNN1	8	L11, M11 N11, P11 P13, R11 R13, R15	BPU1 core power 800 MHz @0.9 V ± 10% 850 MHz @1.0 V + 5%,- 10%
Digital IO Power
VDDPST_ALON	2	G4, H4	General digital IO power 1.8 V ± 10%
VDDPST_ALON_BIFSD	1	R7	BIFSD digital IO power 1.8 V ± 10%
VDDPST_ALON_RGM	1	R9	RGMII digital IO power 1.8 V ± 10%
VDDPST_ALON_BT1120	1	G7	BT1120 OUT digital IO power 1.8 V ± 10%
VDDIO_SD0	1	T11	SD0 digital IO power 3.3 V ± 5% or 1.8 V ± 5%
VDDIO_SD1	1	T13	SD1 digital IO power 3.3 V ± 5% or 1.8 V ± 5%
VDDQ_DDR	8	G15, H15 J15, K15 L15, M15 N15, P15	DDR digital IO power 1.06 V ~ 1.17 V
Analog Power
VDDA_PLL_MAIN	1	K4	PLL analog power for on-chip digital clocking 0.9 V ± 10%
VDDA_PLL_DDR	1	K6	PLL analog power for DDR PHY ref clock 1.8 V ± 10%
VAA_DDR	1	F15	DDR PHY internal PLL analog power 1.8 V ± 5%
VDA_VIO	1	J7	MIPI TX&RX PHY analog power 0.9 V + 10%,- 7%
VDA18_VIO	1	H7	MIPI TX&RX PHY analog power 1.8 V + 10%,- 7%
VDDA_TSEN	1	L6	temperature sensor analog power 1.8 V ± 8%
VQPS_EFUSE	1	G9	EFUSE programming power 1.8 V ± 10%
TACVDD_32K	1	L4	32 kHZ OSC IO analog power 0.9 V ± 10%
Ground
VSS	102	refer to ball map	Digital ground
GD_VIO	7	D3, F3, H3, K3 H6, J6, P1	MIPI TX/RX PHY analog ground
TACVSS_32K	2	M4, P2	32 kHZ OSC IO analog ground

从表中可以看出，电源主要包含数字内核电源、数字IO电源、模拟电源和地。

2.3.2 数字引脚

作为AI芯片，J2的数字引脚是最多的。其中包含调试信号、控制信号、SPI、SD、RGMII、BT1120、UART、I2S、I2C和DDR等。此章节就不具体描述，后续会单独写一篇进行详细讲解。

地平线—征程2（Journey 2-J2）芯片详解（番外篇）—数字引脚-CSDN博客

2.3.3 模拟引脚

J2的模拟引脚主要是MIPI信号，如下表所示：

Pin Name	Ball	Type	Description
MIPI CSI Host RX
MIPI_HOST_CP	H2	AI	MIPI RX clock lane
MIPI_HOST_CN	H1	AI	MIPI RX clock lane
MIPI_HOST_D0P	G3	AI	MIPI RX data lane 0
MIPI_HOST_D0N	G2	AI	MIPI RX data lane 0
MIPI_HOST_D1P	F2	AI	MIPI RX data lane 1
MIPI_HOST_D1N	F1	AI	MIPI RX data lane 1
MIPI_HOST_D2P	E3	AI	MIPI RX data lane 2
MIPI_HOST_D2N	E2	AI	MIPI RX data lane 2
MIPI_HOST_D3P	D2	AI	MIPI RX data lane 3
MIPI_HOST_D3N	D1	AI	MIPI RX data lane 3
MIPI_HOST_REXT	E4	AIO	Connected to calibration resistor on PCB (200ohm ± 1%)
MIPI CSI Device TX
MIPI_DEV_CP	J3	AO	MIPI TX clock lane
MIPI_DEV_CN	J2	AO	MIPI TX clock lane
MIPI_DEV_D0P	K1	AO	MIPI TX data lane 0
MIPI_DEV_D0N	K2	AO	MIPI TX data lane 0
MIPI_DEV_D1P	N2	AO	MIPI TX data lane 1
MIPI_DEV_D1N	N3	AO	MIPI TX data lane 1
MIPI_DEV_D2P	L3	AO	MIPI TX data lane 2
MIPI_DEV_D2N	L2	AO	MIPI TX data lane 2
MIPI_DEV_D3P	M1	AO	MIPI TX data lane 3
MIPI_DEV_D3N	M2	AO	MIPI TX data lane 3
MIPI_DEV_REXT	M3	AIO	Connected to calibration resistor on PCB (200ohm ± 1%)
MIPI Analog Test
MIPI_PHY_ATB	F4	AO	MIPI TX&RX PHY analog test output

2.3.4 电气特性

此部分主要介绍J2芯片不同电源的电压范围，如下表所示：

Symbol	Description	Min	Typ	Max	Unit
Digital Core Power
VDD_CORE_AO	Always On domain core power	0.81	0.9	0.99	V
VDD_CORE_PD	Shut down domain core power	0.81	0.9	0.99	V
VDD_CPU	CPU core power @1GHz	0.81	0.9	0.99	V
	CPU core power @1.25GHz	0.9	1.0	1.05	V
VDD_DDR	DDR Controller & PHY core power @2133Mbps	0.855	0.9	0.945	V
	DDR Controller & PHY core power @2667Mbps	0.95	1.0	1.05	V
VDD_CNN0	CNN0 core power @800MHz	0.81	0.9	0.99	V
	CNN0 core power @850MHz	0.9	1.0	1.05	V
VDD_CNN1	CNN1 core power @800MHz	0.81	0.9	0.99	V
	CNN1 core power @850MHz	0.9	1.0	1.05	V
Digital IO Power
VDDPST_ALON	SYS IO domain power	1.62	1.8	1.98	V
VDDPST_ALON_BIFSD	BIFSD IO domain power	1.62	1.8	1.98	V
VDDPST_ALON_RGMII	RGMII IO domain power	1.62	1.8	1.98	V
VDDPST_ALON_BT11 20OUT	BT1120 OUT IO domain power	1.62	1.8	1.98	V
VDDIO_SD0	SD0 IO domain power @1.8V	1.71	1.8	1.89	V
	SD0 IO domain power @3V	2.85	3	3.15	V
VDDIO_SD1	SD1 IO domain power @1.8V	1.71	1.8	1.89	V
	SD1 IO domain power @3V	2.85	3	3.15	V
VDDQ_DDR	DDR IO domain power	1.06	1.1	1.17	V
Analog Power
VDDA_PLL_MAIN	SYS PLL analog power	0.81	0.9	0.99	V
VDDA_PLL_DDR	DDR PLL analog power	1.62	1.8	1.98	V
VAA_DDR	DDR PHY PLL analog power	1.71	1.8	1.98	V
VDA_VIO	MIPI HOST/DEV PHY 0.9 V analog power	0.837	0.9	0.99	V
VDA18_VIO	MIPI HOST/DEV PHY 1.8 V analog power	1.674	0.9	0.99	V
VDDA_TSEN	Temperature sensor analog power	1.656	1.8	1.944	V
VQPS_EFUSE	EFUSE program analog power	1.62	1.8	1.98	V
TACVDD_32K	32K OSC IO analog power	0.81	0.9	0.99	V
Ground
VSS	Common Ground	/	0	/	V
GD_VIO	MIPI HOST/DEV PHY analog ground	/	0	/	V
TACVSS_32K	32K OSC IO analog ground	/	0	/	V

从表中可以看出，电源主要包含数字内核电源、数字IO电源、模拟电源和地。

2.3.5 温度和热阻

此部分主要介绍J2的结温范围，如下表所示：

Symbol	Description	Min	Typ	Max	Unit
T A	Temperature ambient	-40	/	105	℃
T J	Junction temperature for working	/	/	125	℃

此部分主要介绍J2的热阻参数，如下表所示：

Symbol	Description	Min	Typ	Max	Unit
θ JA	Junction-to-ambient thermal resistance	/	12.22	/	℃/W
θ JB	Junction-to-board thermal resistance	/	8.215	/	℃/W
θ JC	Junction-to-case thermal resistance	/	1.737	/	℃/W
Ψ JT	Junction-to-top thermal characterization parameter	/	1.59	/	℃/W

2.3.6 静电放电等级

此部分主要介绍J2的静电放电参数，如下表所示：

Symbol	Description	Min	Unit
HBM	Human-Body model (HBM)	2000	V
CDM	Charged-device model (CDM)	250	V

总结：本部分分类讲解了J2的PIN脚功能，其中包含电源引脚、数字引脚和模拟引脚，为后续的使用打下了基础。

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