地平线—征程2（Journey 2-J2）芯片详解（1）—芯片概况

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已于 2024-08-19 21:13:26 修改

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分类专栏：智能驾驶AI芯片文章标签：人工智能神经网络深度学习自动驾驶硬件工程嵌入式硬件

于 2024-08-06 22:42:23 首次发布

本文链接：https://blog.csdn.net/eblock/article/details/140967199

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本系列文章主要讲解地平线征程2（Journey 2-J2）芯片的相关知识，希望能帮助更多的同学认识和了解征程2（Journey 2-J2）芯片。

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错过其他章节的同学可以电梯直达目录↓↓↓

地平线—征程2（Journey 2-J2）芯片详解——目录-CSDN博客

1. 芯片概况

1.1 芯片介绍

征程2（Journey 2-J2）是地平线机器人公司研发的一款高性能、低功耗的人工智能（AI）芯片。基于地平线自研的BPU（ Brain Processing Unit )，该方案可以帮助车辆实现高性能的视觉感知，加速智能驾驶的落地。

J2拥有双核Cortex A53，可提供超过 4 TOPS的算力，典型功耗仅 2 瓦，能够高效灵活地实现多类场景任务处理，对多类目标进行实时检测和精准识别。J2 充分体现 BPU 架构强大的灵活性，全方位赋能汽车智能化。

1.2 芯片框图

J2的框图中包含CPU子系统、BPU子系统、DDR子系统、VIO子系统、PMU子系统、并行接口和存储等等。具体详见下图所示：

1.3 芯片特性

芯片的特性如下所示：（还是比较多的 o(╥﹏╥)o）

General

TSMC 28HPC+ (High Performance Compact Plus) Process（高端制程）
FCBGA388 Package with 0.8 mm pitch, 17 mm x 17 mm size（小尺寸）
Automotive AEC-Q100 Grade 2 compliant (operating temperature: -40~105 ℃)（宽温度）
Typical power consumption: 2 W（低功率）
Designed for ADAS and high-level autonomous driving applications（多种应用）

CPU

Dual-core ARM® Cortex® A53, with 32 KB/32 KB L1 I/D cache and 512 KB L2 cache（双核不得了）
Supports FPU and NEON
Separate VDD_CPU voltage domain
1 GHz@VDD_CPU = 0.9 V
Supports Dynamic Voltage and Frequency Scaling (DVFS)
Integrated GIC400 Interrupt Controller
CoreSight debug and trace, including self-hosted debug

BPU

Dual-core Bernoulli-architecture BPU consisting of BPU0 and BPU1（这个是自研的，真自研）
Separate power domain for each core, VDD_CNN0 for BPU0, VDD_CNN1 for BPU1
800 MHz@VDD_CNN* = 0.92 V
Supports Dynamic Voltage and Frequency Scaling (DVFS)
Supports separate power-down for each core
Supports mainstream neural networks
Advanced toolkit supported by Horizon Robotics

DDR

Supports x32 off-chip LPDDR4 DRAM（直接DDR4，高端）
Up to 2 GB capacity
Separate VDD_DDR voltage domain for DDR Controller and DDR PHY
Up to 2133 Mbps@VDD_DDR = 0.9 V
Up to 2667 Mbps@VDD_DDR = 1.0 V
Embedded performance monitor measuring bandwidth, latency, and other metrics on internal bus and DDR Controller, used for debug and performance optimization

Video In/Out and Pre-processing

Supports MIPI CSI video input（MIPI输入）

— 1 clock lane and up to 4 data lanes

— Up to 2.0 Gbps per data lane, peak transmission rate of 8 Gbps over four lanes

— Up to 4096 x 4096 pixels@30fps video input

— Supports RAW 8-/10-/12-/14-bit format and 8-/10-bit YUV 422 format

Supports parallel DVP video input（DVP输入）

— 12-bit data bus interface

— Input clock up to 160 MHz

— Up to 1080P@30fps video input

— Supports RAW 8-/10-/12-/16-/20-bit format and 8-/10-bit YUV 422 format

Supports BT1120 video input（BT1120输入）

— 16-bit data bus interface

— Input clock up to 160 MHz

— Up to 2560 x 1440 pixels@30fps video input

— Only 8-bit YUV 422 format

Inserts Frame_ID into input YUV 422 video stream to synchronize intelligent analysis results and video frames
Supports video in-to-out bypass

— MIPI CSI RX to MIPI CSI TX back-to-back bypass

— DVP IN to DVP OUT feedthrough bypass

— BT1120 IN to BT1120 OUT feedthrough bypass

Supports dual-camera video input through MIPI CSI RX, in side-by-side manner or using 2 virtual channels that requires external chip assistant
Built-in Image Signal Processor (ISP) supporting RAW to YUV conversion, with other image enhancements
Image Processing Unit (IPU)

— Supports cropping and downscaling, storing images into DDR in YUV420 semi-planar format

— Supports dual-camera division, cutting side-by-side images or demultiplexing 2 virtual channels, storing images of each channel into DDR separately

Pyramid (PYM)

— Input images from IPU (online mode) or from DDR (offline mode)

— Input image size up to 2048 x 2048

— Generates multi-layer pyramid images with various dimensions

— Configurable layers, Region of Interest (ROI), and scaling factors

Image display by Intelligent Analysis Result (IAR) via the MIPI CSI TX or BT1120 output interface, with the maximum output of 1080P@60fps, with 1 video layer and 1 UI layer alpha blending

Host Interfaces

Transfer rate for AP SPI master up to 80 MHz (10 MB/s max) using the BIF-SPI slave interface
Transfer mode for AP eMMC Host up to 8-wire HS200 mode (200 MB/s max) using the BIF-SD device interface
BIF-SPI and BIF-SD host interfaces used by AP to access the J2’s DDR, SRAM, and module registers for data exchange and control

Power Management

Flexible clock switching, scaling and gating control
DVFS support for CPU and BPU
BPU0 and BPU1 shutting down respectively.
Supports chip-level sleep mode for maximum power saving, only Always-On (AO) power domain active in sleep mode.
Supports DDR IO retention in sleep mode, with DRAM in self refresh state

Peripheral Interfaces

4x UART

— 2-wire UART0/2/3

— 4-wire UART1 with hardware flow control

— Baud rate up to 921600 bps

3x SPI

— Master mode only

— Up to 50 MHz

2x I2S

— Supports both master and slave modes

— Half duplex for each, configured as RX or TX

— RX supporting1/2/4/8/16-channel audio input

— TX supporting 1/2-channel audio output

— Supports 8/16/32/48KHz sample rate

— Sample rates of I2S0 and I2S1 can be different

4x I2C, only in master mode, up to 400Kbps
9x PWM
1x QSPI

— Only in master mode

— 1/2/4-wire mode, up to 83 MHz

— Mainly used to connect off-chip SPI NOR/NAND Flash

— Supports XIP mode

2x SD3.0/SDIO3.0/eMMC5.0 Host Controller

— SD0 with 8-bit data bus

— SD1 with 4-bit data bus

— Up to HS200 mode

— Uses SD special IO for 3.3 V/1.8 V power switching

1000 Mbps Ethernet MAC Controller, connected to external PHY chip using the RGMII interface
All digital IOs can function as GPIO, and any 4 of them can be selected as interrupt sources or wakeup sources, triggered by positive, negative, or both edges

Others