`timescale 1ns / 1ps
`define clk_en 1
module def_test(
`ifdef clk_en
input clk,
input rst,
output reg[3:0] dout,
`endif
input c,
input b,
input a,
output reg[2:0] decoder
);
wire[2:0] din;
`ifdef clk_en
always @(posedge clk)
if(rst)
dout <= 4'h0;
else if(c)
dout <= dout + 4'h1;
else
dout <= dout;
`endif
assign din = {c,b,a};
always @(din)
case(din)
3'b000: decoder <= 3'b111;
3'b001: decoder <= 3'b110;
3'b010: decoder <= 3'b101;
3'b011: decoder <= 3'b100;
3'b100: decoder <= 3'b011;
3'b101: decoder <= 3'b010;
3'b110: decoder <= 3'b001;
3'b111: decoder <= 3'b000;
default: decoder <= 3'b000;
endcase
endmodule
`timescale 1ns / 1ps
`define clk_en 1
module tb_def_test;
`ifdef clk_en
reg clk;
reg rst;
wire[3:0] dout;
`endif
wire c;
wire b;
wire a;
reg[2:0] test_vector;
wire [2:0] decoder;
`ifdef clk_en
always #12.5 clk = ~clk;
initial begin
clk = 0;
rst = 0;
#200;
rst = 1;
#200;
rst = 0;
end
`endif
assign {c,b,a}=test_vector;
def_test def_test (
`ifdef clk_en
.clk(clk),
.rst(rst),
.dout(dout),
`endif
.c(c),
.b(b),
.a(a),
.decoder(decoder)
);
initial begin
test_vector = 3'b000;
#400;
repeat (20) begin
test_vector = test_vector + 1;
#500;
end
test_vector = 3'b000;
end
endmodule