uboot 启动流程【1】

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已于 2024-04-29 10:04:49 修改

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分类专栏： uboot 文章标签： uboot linux

于 2024-04-29 10:04:18 首次发布

本文链接：https://blog.csdn.net/gang542725/article/details/138281062

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学习资料：https://raw.githubusercontent.com/wowotechX/u-boot/x_integration/README

执行通常从特定于体系结构(也可能是CPU-specific)的启动start.S文件，例如:

	- arch/arm/cpu/armv7/start.S
	- arch/powerpc/cpu/mpc83xx/start.S
	- arch/mips/cpu/start.S

等等......。从那里，调用三个函数;下面描述了这些函数的目的和限制。

arch/arm/cpu/armv8/start.S

12
13/*************************************************************************
14 *
15 * Startup Code (reset vector)
16 *
17 *************************************************************************/
18
19.globl	_start
20_start:
21#if defined(CONFIG_LINUX_KERNEL_IMAGE_HEADER)
22#include <asm/boot0-linux-kernel-header.h>
23#elif defined(CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK)
24/*
25 * Various SoCs need something special and SoC-specific up front in
26 * order to boot, allow them to set that in their boot0.h file and then
27 * use it here.
28 */
29#include <asm/arch/boot0.h>
30#else
31	b	reset
32#endif

reset

55reset:
56	/* Allow the board to save important registers */
57	b	save_boot_params
58.globl	save_boot_params_ret
59save_boot_params_ret:
60
61#if CONFIG_POSITION_INDEPENDENT
62	/* Verify that we're 4K aligned.  */
63	adr	x0, _start
64	ands	x0, x0, #0xfff
65	b.eq	1f
660:
67	/*
68	 * FATAL, can't continue.
69	 * U-Boot needs to be loaded at a 4K aligned address.
70	 *
71	 * We use ADRP and ADD to load some symbol addresses during startup.
72	 * The ADD uses an absolute (non pc-relative) lo12 relocation
73	 * thus requiring 4K alignment.
74	 */
75	wfi
76	b	0b
771:
78
79	/*
80	 * Fix .rela.dyn relocations. This allows U-Boot to be loaded to and
81	 * executed at a different address than it was linked at.
82	 */
83pie_fixup:
84	adr	x0, _start		/* x0 <- Runtime value of _start */
85	ldr	x1, _TEXT_BASE		/* x1 <- Linked value of _start */
86	subs	x9, x0, x1		/* x9 <- Run-vs-link offset */
87	beq	pie_fixup_done
88	adrp    x2, __rel_dyn_start     /* x2 <- Runtime &__rel_dyn_start */
89	add     x2, x2, #:lo12:__rel_dyn_start
90	adrp    x3, __rel_dyn_end       /* x3 <- Runtime &__rel_dyn_end */
91	add     x3, x3, #:lo12:__rel_dyn_end
92pie_fix_loop:
93	ldp	x0, x1, [x2], #16	/* (x0, x1) <- (Link location, fixup) */
94	ldr	x4, [x2], #8		/* x4 <- addend */
95	cmp	w1, #1027		/* relative fixup? */
96	bne	pie_skip_reloc
97	/* relative fix: store addend plus offset at dest location */
98	add	x0, x0, x9
99	add	x4, x4, x9
100	str	x4, [x0]
101pie_skip_reloc:
102	cmp	x2, x3
103	b.lo	pie_fix_loop
104pie_fixup_done:
105#endif
106
107#ifdef CONFIG_SYS_RESET_SCTRL
108	bl reset_sctrl
109#endif
110
111#if defined(CONFIG_ARMV8_SPL_EXCEPTION_VECTORS) || !defined(CONFIG_SPL_BUILD)
112.macro	set_vbar, regname, reg
113	msr	\regname, \reg
114.endm
115	adr	x0, vectors
116#else
117.macro	set_vbar, regname, reg
118.endm
119#endif
120	/*
121	 * Could be EL3/EL2/EL1, Initial State:
122	 * Little Endian, MMU Disabled, i/dCache Disabled
123	 */
124	switch_el x1, 3f, 2f, 1f
1253:	set_vbar vbar_el3, x0
126	mrs	x0, scr_el3
127	orr	x0, x0, #0xf			/* SCR_EL3.NS|IRQ|FIQ|EA */
128	msr	scr_el3, x0
129	msr	cptr_el3, xzr			/* Enable FP/SIMD */
130#ifdef COUNTER_FREQUENCY
131	ldr	x0, =COUNTER_FREQUENCY
132	msr	cntfrq_el0, x0			/* Initialize CNTFRQ */
133#endif
134	b	0f
1352:	set_vbar	vbar_el2, x0
136	mov	x0, #0x33ff
137	msr	cptr_el2, x0			/* Enable FP/SIMD */
138	b	0f
1391:	set_vbar	vbar_el1, x0
140	mov	x0, #3 << 20
141	msr	cpacr_el1, x0			/* Enable FP/SIMD */
1420:
143	isb
144
145	/*
146	 * Enable SMPEN bit for coherency.
147	 * This register is not architectural but at the moment
148	 * this bit should be set for A53/A57/A72.
149	 */
150#ifdef CONFIG_ARMV8_SET_SMPEN
151	switch_el x1, 3f, 1f, 1f
1523:
153	mrs     x0, S3_1_c15_c2_1               /* cpuectlr_el1 */
154	orr     x0, x0, #0x40
155	msr     S3_1_c15_c2_1, x0
156	isb
1571:
158#endif
159
160	/* Apply ARM core specific erratas */
161	bl	apply_core_errata
162
163	/*
164	 * Cache/BPB/TLB Invalidate
165	 * i-cache is invalidated before enabled in icache_enable()
166	 * tlb is invalidated before mmu is enabled in dcache_enable()
167	 * d-cache is invalidated before enabled in dcache_enable()
168	 */
169
170	/* Processor specific initialization */
171	bl	lowlevel_init
172
173#if defined(CONFIG_ARMV8_SPIN_TABLE) && !defined(CONFIG_SPL_BUILD)
174	branch_if_master x0, x1, master_cpu
175	b	spin_table_secondary_jump
176	/* never return */
177#elif defined(CONFIG_ARMV8_MULTIENTRY)
178	branch_if_master x0, x1, master_cpu
179
180	/*
181	 * Slave CPUs
182	 */
183slave_cpu:
184	wfe
185	ldr	x1, =CPU_RELEASE_ADDR
186	ldr	x0, [x1]
187	cbz	x0, slave_cpu
188	br	x0			/* branch to the given address */
189#endif /* CONFIG_ARMV8_MULTIENTRY */
190master_cpu:
191	bl	_main