有限状态机FSM例程

题目

设计一个自动售饮料机的逻辑电路。它的投币口每次只能投入一枚五角或一元的硬币。投入一元五角硬币后给出饮料；投入两元硬币时给出饮料并找回五角。

分析

1、确定输入输出，A=1表示投入一元硬币，B=1表示投入五角硬币，Y=1表示给出饮料，Z=1表示找回五角。
2、确定电路的状态数，投币前初始状态为S0，投入五角硬币为S1，投入一元硬币为S2。

状态图

Verilog代码实现

module fsm_water(
	input			clk,
	input			rst_n,
	input 			a,
	input			b,
	
	output			y,
	output			z
);

parameter	s0 = 2'b00;
parameter	s1 = 2'b01;
parameter	s2 = 2'b10;

reg			[1:0]		state,next_state;

always@(posedge clk) begin
	if(!rst_n)
		state <= s0;
	else
		state <= next_state;
end 

always@(*) begin
	if(!rst_n)
		next_state = s0;
	else begin
		case(next_state)
			s0: begin
				if(a==0 && b==1)
					next_state = s1;
				else if(a==1 && b==0)
					next_state = s2;
				else
					next_state = s0;
			end
			s1: begin
				if(a==0 && b==1)
					next_state = s2;
				else if(a==1 && b==0)
					next_state = s0;
				else 
					next_state = s1;
			end
			s2: begin
				if((a==0 && b==1) || (a==1 && b==0)
					next_state = s0;
				else
					next_state
			end
			default: 
				next_state = s0;
		endcase
	end
end

always@(posedge clk) begin
	if(!rst_n) begin
		y <= 1'b0;
		z <= 1'b0;
	end
	else begin
		case(next_state)
			s0: begin
				y <= 1'b1;
				z <= 1'b0
			end
			s1: begin
				if(a==1 && b==0) begin
					y <= 1'b1;
					z <= 1'b0;
				end
				else begin
					y <= 1'b0;
					z <= 1'b0;
				end
			end
			s2: begin
				if(a==1 && b==0) begin
					y <= 1'b1;
					z <= 1'b1;
				end
				else if(a==0 && b==1) begin
					y <= 1'b1;
					z <= 1'b0;
				end
				else begin
					y <= 1'b0;
					z <= 1'b0;
				end
			end
			default: begin
				y <= 1'b0;
				z <= 1'b0;
			end
		endcase
	end
end


endmodule