module ALU(OP,A,B,F,ZF,CF,OF,SF,PF);
parameter SIZE=32;
output reg[SIZE-1: 0] F;
output CF,ZF,OF,SF,PF;
input[SIZE-1: 0] A,B;
input[3:0] OP;
reg C,ZF,CF,OF,SF,PF;
always@(*)
begin
C=0;
case(OP)
4'b0000:begin F=A&B;end
4'b0001:begin F=A|B;end
4'b0010:begin F=A^B;end
4'b0011:begin F=~(A|B);end
4'b0100:begin {C,F}=A+B;end
4'b0101:begin {C,F}=A-B;end
4'b0110:begin F=A<B;end
4'b0111:begin F=B<<A;end
endcase
ZF=(F==0);
CF=C;
OF=A[SIZE]^B[SIZE]^F[SIZE]^C;
SF=F[SIZE];
PF=~^F;
end
endmodule
module sim_ALU();
parameter SIZE = 32;
wire[SIZE-1:0] F;
wire ZF,OF,SF,PF,CF;
reg[SIZE-1: 0] A,B;
reg [3:0] OP;
integer i;
initial begin
OP=0;
A<=2452;
B<=12;
for(i=0;i<8;i=i+1)
#100 OP=OP+1;
#100 OP=7;
while(OP>0)#100 OP=OP-1;
end
ALU alu(OP,A,B,F,ZF,CF,OF,SF,PF);
endmodule