用电平触发而不用边缘触发可以避免触发器的产生。避免了触发器的产生
module MUX2(rst, clk, Dout);
input rst, clk;
output[7:0] Dout;
reg[7:0] Dout, counter;
always @(posedge clk)
if(rst)
counter = 1;
else if(counter == 188)
counter = 1;
else
counter = counter + 1;
always @(counter)
case(counter)
8'd1 : Dout = 8'h47;
8'd2 : Dout = 8'h1F;
8'd3 : Dout = 8'hFF;
8'd4 : Dout = 8'h10;
default : Dout = 8'h00;
endcase
endmodule