转》【iCore4 双核心板_FPGA】例程十：FSMC总线通信实验——复用地址模式

int main(void)
{
int i;
unsigned int fpga_read_data;

system_clock.initialize();
fsmc.initialize();
led.initialize();

LED_GREEN_ON;

while(1){        
    for(i = 0;i < 256; i++){
        fpga_write(i,i);                                 
    }
    for(i = 0;i < 100000; i++);
    for(i = 0;i < 256;i++){
        fpga_read_data = fpga_read(i);           
        if(fpga_read_data != i){
            LED_GREEN_OFF;
            LED_RED_ON;
        }
    }    
}

}
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module fsmc_ctrl(
input clk_25m,
input pll_100m,
input rst_n,

input FSMC_CLK,
input NADV,
input WRn,
input RDn,
input CSn,
input [23:16]AB,
inout [15:0]DB

);

//--------------------wire---------------------------------//
wire rd = (CSn | RDn);
wire wr = (CSn | WRn);

//--------------------ab-----------------------------------//
reg [23:0]address;

always @ (posedge NADV or negedge rst_n)
    begin
        if(!rst_n)
            begin
                address <= 24'd0;
            end
        else 
            begin
                address <= {AB,DB};
            end
        
    end

//--------------------clk----------------------------------//
reg wr_clk1,wr_clk2;

always @(posedge pll_100m or negedge rst_n)
    begin
        if(!rst_n)
            begin
                wr_clk1 <= 1'd1;
                wr_clk2 <= 1'd1;
            end
        else
            {wr_clk2,wr_clk1} <= {wr_clk1,wr};    //提取写时钟
    end
    
wire clk = (!wr_clk2 | !rd);

//--------------------db_out-------------------------------//
wire [15:0]db_out;
assign DB = !rd ? db_out : 16’hzzzz;

//--------------------my_ram-------------------------------//
my_ram u1(
.address(address),
.clock(clk),
.data(DB),
.wren(!wr),
.rden(!rd),
.q(db_out)
);//例化ram模块

//--------------------endmodule----------------------------//
endmodule