Overview of HDL-Based Design——从HDL开始设计的全过程

 

1.1 Overview of HDL-Based Design

This chapter guides you through a typical HDL-based design procedure using a design of a runner’s stopwatch. The design example used in this tutorial demonstrates many device features, software features, and design flow practices you can apply to your own design. This design targets a Spartan™-3 device; however, all of the principles and flows taught are applicable to any Xilinx® device family, unless otherwise noted.

一句话，设计HDL是关键。

1.2步骤                          

Creating a New Project------ 省略

1.2.1 Design Description

(1)The design used in this tutorial is a hierarchical, HDL-based design, which means that the

top-level design file is an HDL file that references several other lower-level macros. （ HDL 文件是高级，涉及包含到其他低级模块） Thelower-level macros are either HDL modules or IP modules.

(2)The design begins as an unfinished design. Throughout the tutorial, you will complete the design by generating some of the modules from scratch and by completing others from existing files. When the design is complete, you will simulate it to verify the design’s functionality.

 

1.2.1 Design Entry （设计实体）

For this hierarchical design, (1)you will examine HDL files, (2)correct syntax errors, (3)create an HDL macro, and (4)add a CORE Generator module. (5)You will create and use each type of design macro.( 五步：写 hdl 文件，检查改正语法错误，建立一 HDL 宏，添加核心模块（如 IP 模块），建立和使用宏 )

 

1.Creating an HDL-Based Module （这步为写代码，关键）

Using the New Source Wizard and ISE Text Editor （新建文件向导来建立一个文件）

Using the Language Templates （使用语言模板，一定要熟悉会用）

Adding a Language Template to Your File

2.Correcting HDL Errors

3 ． Adding Source Files （抄现成代码，呵呵）

 

4.Creating a CORE Generator Module （配置 CORE Generator 也是个关键）

    CORE Generator is a graphical interactive design tool that enables you to create high-level

modules such as counters, shift registers, RAM and multiplexers. You can customize and

pre-optimize the modules to take advantage of the inherent architectural features of the

Xilinx FPGA architectures, such as Fast Carry Logic, SRL16s, and distributed and block

RAM. 。

   （ 1 ） Creating a CORE Generator Module （ Select IP (Coregen & Architecture Wizard) ）建立一个核心模块，采用 IP 模块创建

   （ 2 ） Instantiating the CORE Generator Module in the HDL Code 核心模块加到 HDL CODE 。

    步骤： Verilog Flow

To instantiate the CORE Generator module using a Verilog flow:

打开工程需要插入 CORE Generator module 的 *.v 文件，光标地位在插入点， Select Edit > Insert File ( 菜单栏 ) and select   you_needed.veo （ CORE Generator module ） . 则插入相应 CORE Generator module 的模块名，改为需要的模块名，并改端口名使与 HDL 文件对应。

5.Creating a DCM Module

The Clocking Wizard, a part of the Xilinx Architecture Wizard, enables you to graphically

select Digital Clock Manager (DCM) features that you wish to use. In this section you

create a basic DCM module with CLK0 feedback and duty-cycle correction.

步骤

1．            同 4 。 Creat a Core Generator Module 的步骤（ 1 ）

2.    Instantiating the DCM Macro - Verilog

类似 4 。 Creat a Core Generator Module ，但有不同，详细见《 ise 深入指南 》

经过以上步骤，我们已经把一个具有所想要功能的设计文件设计好了。以后是 XST 以及配置，仿真，等过程。

可以看出，要用 FPGA 设计出一个良好的 HDL 描述功能的数字系统，需要 Creating an HDL-Based Module 和配置 CORE Generator 。要考虑代码最小最佳硬件资源利用。

 

 

 

 

1.2.2 Synthesizing the Design （综合设计）

    这步的作用 : HDL-Based Design--------- 》 Design Implementation

 

So far you have been using XST (the Xilinx synthesis tool) for syntax checking. Next, you

will synthesize the design using either XST 。 The synthesis tool uses the design’s HDL code and generates a supported netlist

type (EDIF or NGC) for the Xilinx implementation tools. The synthesis tool performs three

general steps (although all synthesis tools further break down these general steps) to create the netlist:

（ 1 ） Analyze / Check Syntax

Checks the syntax of the source code.

（ 2 ） Compile

Translates and optimizes the HDL code into a set of components that the synthesis tool

can recognize. （把 HDL CODE 转为综合开发工具可识别）

（ 3 ） Map （建立网表）

Translates the components from the compile stage into the target technology’s

primitive components.

步骤

 

   1 ．选择综合开发工具 synthesis tool ： XST （只用这个）

2. Synthesizing the Design using XST

During synthesis, the HDL files are translated into gates and optimized to the

target architecture. 步骤为：

Processes available for synthesis using XST are as follows:

（ 1 ） • View Synthesis Report

Gives a synthesis mapping and timing summary as well as optimizations that took

place.

（ 2 ） • View RTL Schematic

Generates a schematic view of your RTL netlist.

（ 3 ） • View Technology Schematic

Generates a schematic view of your Technology netlist.

（ 4 ） • Check Syntax

Verifies that the HDL code is entered properly.

（ 5 ） • Generate Post-Synthesis Simulation Model

Creates HDL simulation models based on the synthesis netlist .

 

Entering Constraints

XST supports a User Constraint File (UCF) style syntax to define synthesis and timing

constraints. This format is called the Xilinx Constraint File (XCF), and the file has an .xcf

file extension. XST uses the .xcf extension to determine if the file is a constraints file.

 

 

Entering Synthesis Options

Synthesis options enable you to modify the behavior of the synthesis tool to make

optimizations according to the needs of the design. One commonly used option is to

control synthesis to make optimizations based on area or speed. Other options include

controlling the maximum fanout of a signal from a flip-flop or setting the desired

frequency of the design.

 

Synthesizing the Design

Now you are ready to synthesize your design. To take the HDL code and generate a

compatible netlist:

 

The RTL / Technology Viewer

XST can generate a schematic representation of the HDL code that you have entered. A

schematic view of the code helps you analyze your design by displaying a graphical

connection between the various components that XST has inferred. There are two forms of

the schematic representation:

• RTL View - Pre-optimization of the HDL code.

• Technology View - Post-synthesis view of the HDL design mapped to the target

technology.

 

 

You have completed XST synthesis. An NGC file now exists for the Stopwatch design.

这就是说完成了前面所有的流程，此后流程为行为仿真 Behavioral Simulation 和设计实现 Design Implementation

To continue with the HDL flow:

• Go to Chapter 4, “Behavioral Simulation,” to perform a pre-synthesis simulation of

this design.

OR

• Proceed to Chapter 5, “Design Implementation,” to place and route the design.

 

 

2．          Behavioral Simulation

 

2.1Overview of Behavioral Simulation Flow

Xilinx ISE Simulator that allows simulations to be run from the Xilinx Project Navigator.

The examples in this tutorial demonstrate how to use the integrated flow. （有两种仿真软件， Mentor ModelSim simulator and the Xilinx ISE Simulator ，只学后一种）

2.2Getting Started

The following sections outline the requirements for performing behavioral simulation in

this tutorial.

2.2.1 ． Required Files

The behavioral simulation flow requires design files, a test bench file, and Xilinx

simulation libraries.

 

Design Files (VHDL, Verilog, or Schematic)--- 这步以做好

 

Test Bench File---- 本节所要说明的

In order to simulate the design, a test bench file is required to provide stimulus to the

design.

 

Xilinx Simulation Libraries

Xilinx simulation libraries are required when any Xilinx primitive is instantiated in the

design. The design in this tutorial requires the use of simulation libraries because it

contains instantiations of a digital clock manager (DCM) and a CORE Generator™

component.----- 不是必须，但是当你包含 Xilinx 的 IP 模块这就必须。

2.2.2 Xilinx Simulation Libraries

To simulate designs that contain instantiated Xilinx primitives or CORE Generator

components, you must use the Xilinx simulation libraries. These libraries contain models

for each component. These models reflect the functions of each component, and provide

the simulator with the information required to perform simulation.

Updating the Xilinx Simulation Libraries

The Xilinx simulation libraries contain models that are updated on a regular basis.

• The XilinxCoreLib models are updated each time an IP Update is installed.

• All other models are updated each time a service pack is installed.

When the models are updated, you must recompile the libraries. The compiled Xilinx

simulation libraries are then available during the simulation of any design.

2 ． 3Adding an HDL Test Bench

In order to add an HDL test bench to your design project, you can either add a test bench

file provided with this tutorial, or create your own test bench file and add it to your project.

2.3.1 Create your own test bench file

（ 1 ）以文本方式建立 TEST BENCH FILE

To create your own test bench file in ISE, select Project > New Source , and select either

VHDL Test Bench or Verilog Text Fixture in the New Source Wizard. An empty stimulus file is

added to your project. You must define the test bench in a text editor.

（ 2 ） Creating a Test Bench Waveform Using the Waveform Editor

     以创建波形方式实现仿真。

This section demonstrates how to use the Waveform Editor. The Waveform Editor is a test

bench creation tool in ISE. You can use the Waveform Editor to graphically enter stimuli,

and to generate a VHDL test bench or Verilog test fixture. It is not necessary to follow this

section if you have added the tutorial test bench to the project already.

当你已经实现（ 1 ）时这步就没必要了。二者并列。

      Creating a Test Bench Waveform Source

In this tutorial, create the test bench waveform for a sub-module only. The Waveform

Editor can be used to generate stimuli for top-level designs as well.

 

Applying Stimulus

In the Waveform Editor, in the blue cell, you can apply a transition (high/low). The

of this cell is determined by the Input setup delay and the Output valid delay.

 

Now, when either Behavioral or Timing simulation is run, the simulation output is

automatically checked against the expected result.

 

 

------------------ 学会建立

2.3.2A dding Tutorial Test Bench File

This section demonstrates how to add pre-existing test bench file to the project.

------------------- 利用别人写的现成的。

2.4Behavioral Simulation Using ISE Simulator

2.4.1 用 ISE Simulator 仿真的步骤。

Now that you have a test bench in your project, you can perform behavioral simulation on

the design using the ISE Simulator. ISE has full integration with the ISE Simulator. ISE

enables ISE Simulator to create the work directory, compile the source files, load the

design, and perform simulation based on simulation properties.

（ 1 ） Locating the Simulation Processes （定位仿真过程）

The simulation processes in ISE enable you to run simulation on the design using ISE

Simulator. To locate the ISE Simulator processes:

The following simulation processes are available:

• Check Syntax

• Simulate Behavioral Model

This process starts the design simulation.

• Generate Expected Simulation Results

This process is available only if you have a test bench waveform file from ISE

Simulator’s Test Bench Waveform Editor. If you run this process, the ISE Simulator

runs in the background to generate expected results and displays them in the

Waveform Editor.

 

（ 2 ） Specifying Simulation Properties （指明仿真参数）

You will perform a behavioral simulation on the stopwatch design after you set some

process properties for simulation.

ISE allows you to set several ISE Simulator properties in addition to the simulation netlist

properties.

（ 3 ） Performing Simulation

Once the process properties have been set, you are ready to run the ISE Simulator. To start

the behavioral simulation, double-click Simulate Behavioral Model . ISE Simulator creates

the work directory, compiles the source files, loads the design, and performs simulation for

the time specified.

（ 4 ） Adding Signals

To view signals during the simulation, you must add them to the Waveform window. ISE

automatically adds all the top-level ports to the Waveform window. Additional signals are

displayed in the Sim Hierarchy window. The following procedure explains how to add

additional signals in the design hierarchy. For the purpose of this tutorial, add the DCM

signals to the waveform.

（ 5 ） Rerunning Simulation （再次仿真）

 

Your behavioral simulation is complete. To implement the design, follow the steps in

Chapter 5, “Design Implementation.”

至此，仿真结束

 

3 ． Design Implementation

3.1Overview of Design Implementation

Design Implementation is the process of translating, mapping, placing, routing, and

generating a BIT file for your design. The Design Implementation tools are embedded in

the ISE™ software for easy access and project management.

3.2Getting Started

两种作法：

3.2.1 Continuing from Design Entry

If you have followed the tutorial using either the HDL Design flow or the Schematic

Design flow, you have created a project, design entry source files, and an EDIF netlist file.

从 HDL 设计流程（或从 the Schematic Design flow ） 开始设计，然后执行到 Design Implementation

3.2.2 Starting from Design Implementation

利用已有的。 the presynthesized design files provided on the Xilinx ® website

3.3Specifying Options

This section describes how to set some properties for design implementation. The

implementation properties control how the software maps, places, routes, and optimizes a

design.

3.4Creating Partitions

implementation for that instance should be reused when possible. Partitions can be nested

hierarchically and be defined on any HDL module instance in the design. In Verilog, the

partition is set on the module instance and for VHDL, the partition is set on the entity

architecture. A module with multiple instances can have multiple partitions—a partition

on each instance. The top level of the HDL design has a default partition.

Partitions do not need ranges for implementation re-use, and logic can be at the top level

partition. Partitions automatically detect input source changes, including HDL changes

and certain constraint changes. Partitions also detect command line changes, such as effort

levels on implementation tools, and only the effected partitions are re-implemented.

3.4Creating Timing Constraints

The User Constraints File (UCF) provides a mechanism for constraining a logical design

without returning to the design entry tools. However, without the design entry tools, you

must understand the exact syntax needed to define constraints. The Constraints Editor and

Pinout Area Constraints Editor (PACE) are graphical tools that enable you to enter timing

and pin location constraints

3.5Translating the Design

ISE manages the files created during implementation. The ISE tools use the settings that

you specified in the Process Properties dialog box. This gives you complete control over

how a design is processed. Typically, you set your options first. You then run through the

entire flow by double-clicking Implement Design . This tutorial illustrates the

implementation, one step at a time.

During translation, the NGDBuild program performs the following functions:

• Converts input design netlists and writes results to a single merged NGD netlist. The

merged netlist describes the logic in the design as well as any location and timing

constraints.

• Performs timing specification and logical design rule checks.

• Adds the User Constraints File (UCF) to the merged netlist.

3.6Using the Constraints Editor

When you run the Create Timing Constraints process, Translate is run and ISE launches the

Constraints Editor.

The Constraints Editor enables you to:

• Edit constraints previously defined in a UCF file.

• Add new constraints to your design.

Input files to the Constraints Editor are:

• NGD (Native Generic Database) File

The NGD file serves as input to the mapper, which then outputs the physical design

database, an NCD (Native Circuit Description) file.

• Corresponding UCF (User Constraint File)

By default, when the NGD file is opened, an existing UCF file with the same base name

as the NGD file is used. Alternatively, you can specify the name of the UCF file.

The Constraints Editor generates a valid UCF file. The Translate step (NGDBuild) uses the

UCF file, along with design source netlists, to produce a newer NGD file, which

incorporates the changes made.

3.7Using the Pin-out Area Constraints Editor (PACE)

 

 补档中！！！！！！！！！！！！！！！！！！！！！！！！！！！！！！！