刚新键一项目时显示说明:
Project:
Project Name: wtut_ver------名称
Project Path: D:/verilog/verilog/wtut_ver-----路径
Top Level Source Type: HDL
Project Name: wtut_ver------名称
Project Path: D:/verilog/verilog/wtut_ver-----路径
Top Level Source Type: HDL
Device:-----硬件描述
Device Family: Spartan3
Device: xc3s200
Package: ft256
Speed: -4
Device Family: Spartan3
Device: xc3s200
Package: ft256
Speed: -4
Synthesis Tool: XST (VHDL/Verilog)----xilinx综合开发工具
Simulator: ISE Simulator (VHDL/Verilog)----模拟,仿真
Simulator: ISE Simulator (VHDL/Verilog)----模拟,仿真
Enhanced Design Summary: enabled
Message Filtering: disabled
Display Incremental Messages: disabled
Message Filtering: disabled
Display Incremental Messages: disabled
Existing Sources:-----填加文件
stopwatch.v
clk_div_262k.v
debounce.v
led_control.v
statmach.v
//
stopwatch.v
clk_div_262k.v
debounce.v
led_control.v
statmach.v
//
哈哈,明白了。这是一种用命令的方式创建工程文件,我压的还以为是另一种创建方式的后继步骤。
Creating a New Project: Using a Tcl Script------不理解这步的意思,好象是显示各种方式对工程文件做了什么操作。以及可以直接 用他的命令来对工程文件做操作。
1. With Project Navigator open, select the Tcl Console tab.
下面是改工程目录到当前工程目录,其作用可能是使以后创建的文件都在这目录下
2. Change the current working directory to the directory where the tutorial source files
were unzipped by typing r “cd c:/xilinx/ISEexamples/wtut_ver” (Verilog design entry).-----注意一定要是“/”
2. Change the current working directory to the directory where the tutorial source files
were unzipped by typing r “cd c:/xilinx/ISEexamples/wtut_ver” (Verilog design entry).-----注意一定要是“/”
在这目录下可以用命令的方式创建文件?(不对,下面这条命令的作用是其他)
3. Run the project creation Tcl script by typing “source create_wtut_ver.tcl” (Verilog design entry).
Note: If presented with a dialog box stating that *.ise appears to be locked, click Yes to continue
project creation.
3. Run the project creation Tcl script by typing “source create_wtut_ver.tcl” (Verilog design entry).
Note: If presented with a dialog box stating that *.ise appears to be locked, click Yes to continue
project creation.
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All procedures used in the tutorial can be used later for your own designs.
步骤是:
Design Description:Inputs;Outputs;Functional Blocks;
Design Entry:Adding Source Files;
Checking the Syntax;
Correcting HDL Errors;
Creating an HDL-Based Module
{Using the New Source Wizard and ISE Text Editor
Using the Language Templates};
Creating a CORE Generator Module;
Creating a DCM Module;-----------Digital Clock Manager (DCM)
Synthesizing the Design;
Synthesizing the Design using XST;
Synthesizing the Design using Synplify/Synplify Pro;
Synthesizing the Design using LeonardoSpectrum;
先看到这。睡觉了。
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