用FPGA实现8'bitSRAM读写控制的Verilog代码

`define SRAM_SIZE 8
`timescale 1ns/1ns
//FOR SRAM INTERFACE CONTROL
module SRAM_INTERFACE(in_data,//INPUT DATA
            out_data,//OUTPUT DATA
            fiford,//FIFO READ CONTROL LOW VOLTAGE
            fifowr,//FIFO WRITE CONTROL LOW VOLTAGE
            nfull,
            nempty,
            address,//SENT SRAM ADDRESS BUS
            sram_data,//SRAM DATA BUS
            rd,//SRAM READ SINGAL ENABLE LOW VOLTAGE
            wr,//SRAM WRITE ENABLE LOW VOLTAGE
            clk,//system clk
            rst);//global reset singal,low voltage
input  fiford,fifowr,clk,rst;
input[7:0] in_data;
output[7:0] out_data;
reg[7:0]  in_data_buf,out_data_buf;//input and output buffer
output  reg  nfull,nempty;
output rd,wr;
inout[7:0] sram_data;
output reg [10:0]address;
reg[10:0] fifo_wp,fifo_rp;
reg[10:0]fifo_wp_next,fifo_rp_next;
reg near_full,near_empty;
reg[3:0] state;

parameter idle=4'b0000,
          read_ready='b0100,
          read='b0101,
          read_over='b0111,
          write_ready='b1000,
          write='b1001,
          write_over='b1011;

always@(posedge clk or negedge rst)
begin
      if(!rst)
          state<=idle;
       else case(state)
               idle:begin
                    if(fifowr==0&&nfull)
                     state<=write_ready;
                   else if(fiford==0&&nempty)
                     state<=read_ready;
                   else
                     st