用verilog设计一个交通信号灯，要求有红，黄，绿，左转四盏灯

设计一交通灯系统，要求有红，黄，绿，左转四盏灯，并且每个路口有需要一个倒数的计数器，绿灯维持的时间为 40 秒，黄灯为 5 秒，左转灯 10 秒，红灯 60 秒。要求在 modelsim 仿真波形中显示至少一个完整的交通灯变换周期，顺序是先绿灯，再黄灯，最后左转灯和红灯同时亮。

程序在modelsim中运行和仿真

源程序如下：

<div>module traffic(clk,rset,count_g,count_d,green,yellow,turnleft,red);
  input clk,rset;
  output[3:0] count_g,count_d;//计数器的高位，计数器的低位
  wire[3:0] count_g,count_d;
  output green,yellow,red,turnleft;//绿、黄、红、左转灯
  reg green,yellow,turnleft,red;
  reg[31:0] qout;//寄存器，用来暂存十进制的计数值
  always @(posedge clk)//控制绿灯亮灭
  begin
    if(!rset)
      begin
        green<=1;
        qout<=39;
      end
    else if(yellow==0&&red==0)
      begin
       if(qout>0)
         qout<=qout-1;
       else
         begin
         green<=0;//绿灯灭
         qout<=4;//给黄灯计数器赋值
         yellow<=1;//让黄灯亮起来
         end
     end
  end
  
  always @(posedge clk)//控制黄灯亮灭
  begin
    if(!rset) yellow<=0;
    else if(green==0&&red==0)
      begin
        if(qout!=0)
          qout<=qout-1;
        else
          begin
            red<=1;//让红灯亮
            turnleft<=1;//让左转灯亮
            yellow<=0;//黄灯灭
            qout<=59;//给红灯和左转灯计数器赋值
          end
      end
  end
  
  always @(posedge clk)//控制红灯亮灭状态
  begin
    if(!rset) red<=0;
    else if(green==0&&yellow==0)
      begin
        if(qout>0)
          qout<=qout-1;
        else
          begin
            red<=0;//红灯灭
            qout<=39;//给绿灯计数器赋值
            green<=1;//绿灯亮
          end
      end
  end</div><div>
</div><div> always @(posedge clk)//控制左转灯亮灭
 begin
   if(!rset) turnleft<=0;
   else if(green==0&&yellow==0&&qout<51)//控制左转灯亮10s后熄灭
     turnleft<=0;
end</div><div>
</div><div>assign count_g=qout/10;//给计数器高位从暂存计数器取值
assign count_d=qout%10;//给计数器低位从暂存计数器取值</div><div>
</div><div>endmodule</div>

测试程序如下：

`timescale 1ns/1ns
module traffic_tb();
  reg clk,rset;
  wire[3:0] count_g,count_d;
  wire green,yellow,turnleft,red;
  parameter DELY=100;
  traffic u1(.clk(clk),.rset(rset),.count_g(count_g),.count_d(count_d),
             .green(green),.yellow(yellow),.turnleft(turnleft),.red(red));
  always #(DELY/2) clk=~clk;
  initial
  begin
    clk=0;rset=0;
    #DELY rset=1;
    #(DELY*10000) $finish;
  end
  initial $monitor($time,,,"clk=%d,rset=%d,count_g=%d,count_d=%d,green=%d,yellow=%d,turnleft=%d,red=%d",
                      clk,rset,count_g,count_d,green,yellow,turnleft,red);
endmodule