imx53笔记

1，CCM

 CCM_CLK_IGNITION ：reset后

CCM_CLK_ SWITCHER ：输入时钟是4个DPLL,输出时钟：pll1_sw_clk，pll2_sw_clk，pll3_sw_clk，pll4_sw_clk

CCM_CLK_ROOT_GEN ：输入时钟：pllx_sw_clk,输出：root clocks

（DPLL-1 (typical functional frequency 800Mhz： supply ARM platform) 

• DPLL-2 (400Mhz：supply axi/ahb/ip buses) 

• DPLL-3 ( 216Mhz：supply serial clocks likeusb, ssi)

• DPLL-4 ( 595Mhz：supply LDB clocks））
DPLL1 - initial value =192Mhz
DPLL2 - initial value = 192Mhz
DPLL3 - initial value = 168Mhz
DPLL4 - initial value = 168Mhz

CCM_CBCMR寄存器：11–10 bit DDR_CLK_SEL[1:0]
Selector for DDR clock multiplexer
00 derive clock from axi a (Default)
01 derive clock from axi b
10 derive clock from emi_slow_clk_root
11 derive clock from ahb clock root

EIM_CS0GCR1，EIM_CS1GCR1 

    18–16 DSZ：11 32位数据

    13–12 BCD：00 Divide EIM clock by 1；  01 Divide EIM clock by 2

    3： MUM

2，DDR

Column size between 9 to 11 bits;    Row size between 11 to 16 bits;  Burst length 8 for DDR3 devices.;  frequency 303 MHz to 400 MHz

EXTMC supports Little endian only

 x8 devices are not supported in EXTMC

 It provides a direct interface to both 8-bit and 16-bit NAND Flash