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最新推荐文章于 2024-04-24 18:00:00 发布

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最新推荐文章于 2024-04-24 18:00:00 发布

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本文介绍了一项使用VHDL语言设计的多功能电子钟项目，包括24小时制电子时钟、秒表和定时器功能。通过QuartusII进行编译、综合并在实验板上实现。电子钟支持分屏显示时间和切换显示模式，秒表精度为0.01秒，定时器可设置0~9999秒。用户通过按键进行操作，如设置时间、切换模式、暂停/继续及清零。项目包含顶层文件、分频、消抖、时钟、秒表、定时器和显示功能的详细设计，并提供了操作说明和仿真/实验结果。

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用VHDL语言设计多功能电子钟，用QuartusII工具编译和综合，并在实验板上调试并实现所要求功能和技术指标，撰写实验报告，最后提交验收并答辩。

题目：多功能电子钟。主要功能要求：

1、电子时钟。要求用24时制显示。分屏显示“时、分”和“分、秒”，即4个数码管不能同时显示“时、分、秒”，但可以只显示“时、分”，或只显示“分、秒”，通过按键来切换这两种显示方式。用数码管的小数点“.”代替时、分、秒的分隔符“：”。可设置时间。设置时间时，当前设置的“时”/“分”，相应的数码管应闪烁。

2、秒表（计时器）。秒表精度为0.01秒，计时范围0~99.99秒，用4个数码管显示，两个显示秒，两个显示百分秒，有暂停/继续、重置（清零）按钮。

3、定时器。可以实现0~9999秒定时。设置一定时值，当计时到达设定值时输出LED闪烁。有设置、暂停/继续、清零定时按钮。

1.顶层文件

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.All;


ENTITY zongshe IS
PORT(clk,key1,key2,key3,key4,key5:IN STD_LOGIC;
     seg7data: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
	  seg7com: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
	  led:OUT STD_LOGIC);
END ENTITY zongshe;

ARCHITECTURE behav OF zongshe IS

COMPONENT fenpin IS
PORT(clk:IN STD_LOGIC;
      clk1s:OUT STD_LOGIC;
		clk01s:OUT STD_LOGIC;
		clk001s:OUT STD_LOGIC;
		clk0001s:OUT STD_LOGIC);
END COMPONENT fenpin;


COMPONENT xiaodoutongji IS
 PORT(mod_key5:IN STD_LOGIC;
      set_key1:IN STD_LOGIC;
		shang_key2:IN STD_LOGIC;
		ok_key3:IN STD_LOGIC;
		clr_key4:IN STD_LOGIC;
		key5num:BUFFER INTEGER;
      key1num:BUFFER INTEGER;
		key2num:BUFFER INTEGER;
		key3num:BUFFER INTEGER;
		key4num:BUFFER INTEGER;
		clk:IN STD_LOGIC);
 END COMPONENT xiaodoutongji;
 
 
COMPONENT clock IS
PORT(clk0001s:IN STD_LOGIC;
  key3num:IN INTEGER:=0;
  key5num:IN INTEGER:=0;
  key1num:IN INTEGER:=0;
  key2num:IN INTEGER:=0;
  clknum1,clknum2,clknum3,clknum4:BUFFER INTEGER:=0);
END COMPONENT clock;

COMPONENT miaobiao IS
PORT(clk001s:IN STD_LOGIC;
     key5num,key2num,key4num:IN INTEGER;
     miaobiaonum1:BUFFER INTEGER;
	  miaobiaonum2:BUFFER INTEGER;
	  miaobiaonum3:BUFFER INTEGER;
	  miaobiaonum4:BUFFER INTEGER);
END COMPONENT miaobiao;

COMPONENT xianshi IS
PORT(clk0001s:IN STD_LOGIC;
     key1num,key5num,key2num:IN INTEGER;
	  clknum1,clknum2,clknum3,clknum4:IN INTEGER;
	  mbnum1,mbnum2,mbnum3,mbnum4:IN INTEGER:=0;
	  dingnum1,dingnum2,dingnum3,dingnum4:IN INTEGER:=0;
	  com:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
	  data:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END COMPONENT xianshi;

COMPONENT dingshiqi IS
PORT(clk0001s:IN STD_LOGIC;
     key5num,key1num,key2num,key3num,key4num:IN INTEGER;
     dingnum1,dingnum2,dingnum3,dingnum4:BUFFER INTEGER;
	  led:BUFFER STD_LOGIC);
END COMPONENT dingshiqi;




SIGNAL sys_clk1s:STD_LOGIC;
SIGNAL sys_clk01s:STD_LOGIC;
SIGNAL sys_clk001s:STD_LOGIC;
SIGNAL sys_clk0001s:STD_LOGIC;
SIGNAL sys_key1num:INTEGER:=0;
SIGNAL sys_key2num:INTEGER:=0;
SIGNAL sys_key3num:INTEGER:=0;
SIGNAL sys_key4num:INTEGER:=0;
SIGNAL sys_key5num:INTEGER:=0;
SIGNAL sys_clknum1:INTEGER:=0;
SIGNAL sys_clknum2:INTEGER:=0;
SIGNAL sys_clknum3:INTEGER:=0;
SIGNAL sys_clknum4:INTEGER:=0;
SIGNAL sys_mbnum1:INTEGER:=0;
SIGNAL sys_mbnum2:INTEGER:=0;
SIGNAL sys_mbnum3:INTEGER:=0;
SIGNAL sys_mbnum4:INTEGER:=0;
SIGNAL sys_dingnum1:INTEGER:=0;
SIGNAL sys_dingnum2:INTEGER:=0;
SIGNAL sys_dingnum3:INTEGER:=0;
SIGNAL sys_dingnum4:INTEGER:=0;

BEGIN

fp:fenpin PORT MAP(clk=>clk,clk1s=>sys_clk1s,clk01s=>sys_clk01s,
                   clk001s=>sys_clk001s,clk0001s=>sys_clk0001s);
xd:xiaodoutongji PORT MAP(mod_key5=>key5,set_key1=>key1,
                          shang_key2=>key2,ok_key3=>key3,
								  clr_key4=>key4,key1num=>sys_key1num,
								  key2num=>sys_key2num,key3num=>sys_key3num,
								  key4num=>sys_key4num,key5num=>sys_key5num,clk=>clk);
								  
ck:clock	PORT MAP(clk0001s=>sys_clk0001s,key1num=>sys_key1num,
								  key2num=>sys_key2num,
								  key3num=>sys_key3num,
								  key5num=>sys_key5num,
								  clknum1=>sys_clknum1,clknum2=>sys_clknum2,clknum3=>sys_clknum3,
						        clknum4=>sys_clknum4);							  

mb:miaobiao PORT MAP(clk001s=>sys_clk001s,key2num=>sys_key2num,key4num=>sys_key4num,
                     key5num=>sys_key5num,miaobiaonum1=>sys_mbnum1,
	                  miaobiaonum2=>sys_mbnum2,miaobiaonum3=>sys_mbnum3,
							miaobiaonum4=>sys_mbnum4);
ds:dingshiqi PORT MAP(clk0001s=>sys_clk0001s,key1num=>sys_key1num,
							key2num=>sys_key2num,key3num=>sys_key3num,
							key4num=>sys_key4num,key5num=>sys_key5num,
							dingnum1=>sys_dingnum1,dingnum2=>sys_dingnum2,
							dingnum3=>sys_dingnum3,dingnum4=>sys_dingnum4,led=>led);
							
							
								  
								  
xs:xianshi PORT MAP(clk0001s=>sys_clk0001s,key1num=>sys_key1num,key5num=>sys_key5num,
                    key2num=>sys_key5num,
                    clknum1=>sys_clknum1,clknum2=>sys_clknum2,clknum3=>sys_clknum3,
						  clknum4=>sys_clknum4,mbnum1=>sys_mbnum1,mbnum2=>sys_mbnum2,
						  mbnum3=>sys_mbnum3,mbnum4=>sys_mbnum4,
						  dingnum1=>sys_dingnum1,dingnum2=>sys_dingnum2,
						  dingnum3=>sys_dingnum3,