三态门 LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; ENTITY tri_gate IS PORT(DIN,EN:IN std_logic; DOUT: OUT std_logic); END tri_gate; EN=0,输出为高阻态 EN=1,输出等于输入 ARCHITECTURE rtl OF tri_gate IS BEGIN PROCESS(DIN,EN) BEGIN IF(EN='1') THEN DOUT<=DIN; ELSE DOUT<='Z'; END IF; END PROCESS; END rtl;