Xilinx Spartan6-XC6SLX16-22FTG256 （2022.3.30）

最新推荐文章于 2023-07-12 14:14:08 发布

jy_jiangyan

最新推荐文章于 2023-07-12 14:14:08 发布

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分类专栏：赛灵思fpga 文章标签： fpga开发

本文链接：https://blog.csdn.net/jy_jiangyan/article/details/123849474

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注意事项：

1、{ ，}位拼接运算符（两个数之间中间用“，”隔开，也可以有多个“，”进行更多位的拼接；

2、wire为输入型变量，reg为输出型变量，在实际工程中input 必须为wire型，输出可以为wire也可以为reg型。但wire型输出不能出现在always中，只能配合assign使用，如半加器例子

一、LED灯

module led_test(key,led);
	input   wire[3:0]  key;            
	output  reg[3:0]  led;

always@(*)
	begin
		led=~key;
	end
endmodule

ucf文件

NET led<0>                LOC = P4 | IOSTANDARD = "LVCMOS33";       ## LED1
NET led<1>                LOC = N5 | IOSTANDARD = "LVCMOS33";       ## LED2
NET led<2>                LOC = P5 | IOSTANDARD = "LVCMOS33";       ## LED3
NET led<3>                LOC = M6 | IOSTANDARD = "LVCMOS33";       ## LED4
NET key<0>                LOC = C3 | IOSTANDARD = "LVCMOS33";       ## KEY1
NET key<1>                LOC = D3 | IOSTANDARD = "LVCMOS33";       ## KEY2
NET key<2>                LOC = E4 | IOSTANDARD = "LVCMOS33";       ## KEY3
NET key<3>                LOC = E3 | IOSTANDARD = "LVCMOS33";       ## LED4

二、三八译码器

module led_test(
	input   wire  		key1, 
	input   wire  		key2,  
	input   wire  		key3, 
	input   wire  		key4,   	
	output  reg[3:0]  led
);
always@(*)
	case({key1,key2,key3,key4})
		4'b1111:led=4'b1000;
		4'b1101:led=4'b0100;
		4'b1011:led=4'b0010;
		4'b1110:led=4'b0001;
		default:led=4'b0000;
	endcase
endmodule

ucf文件

NET led<0>                LOC = P4 | IOSTANDARD = "LVCMOS33";       ## LED1
NET led<1>                LOC = N5 | IOSTANDARD = "LVCMOS33";       ## LED2
NET led<2>                LOC = P5 | IOSTANDARD = "LVCMOS33";       ## LED3
NET led<3>                LOC = M6 | IOSTANDARD = "LVCMOS33";       ## LED4
NET key1                  LOC = C3 | IOSTANDARD = "LVCMOS33";       ## KEY1
NET key2                  LOC = D3 | IOSTANDARD = "LVCMOS33";       ## KEY2
NET key3                  LOC = E4 | IOSTANDARD = "LVCMOS33";       ## KEY3
NET key4                  LOC = E3 | IOSTANDARD = "LVCMOS33";       ## LED4

三、半加器

module led_test(
   input wire         key1,
   input wire         key2,
   input wire         key3,
   input wire         key4,
   //output wire[3:0] led
   output reg[3:0] led
);
//assign led=key1+key2+key3+key4;

always@(*)
   begin
   led<=key1+key2+key3+key4;
   end

endmodule

ucf文件

NET led<0>              LOC = P4 | IOSTANDARD = "LVCMOS33";       ## LED1
NET led<1>              LOC = N5 | IOSTANDARD = "LVCMOS33";       ## LED2
NET led<2>              LOC = P5 | IOSTANDARD = "LVCMOS33";       ## LED3
NET led<3>              LOC = M6 | IOSTANDARD = "LVCMOS33";       ## LED4
NET key1                LOC = C3 | IOSTANDARD = "LVCMOS33";       ## KEY1
NET key2                LOC = D3 | IOSTANDARD = "LVCMOS33";       ## KEY2
NET key3                LOC = E4 | IOSTANDARD = "LVCMOS33";       ## KEY3
NET key4                LOC = E3 | IOSTANDARD = "LVCMOS33";       ## LED4