For 8155
pls follow below steps to enable spi dma mode:
1. change the qnx_ap/boards/core/dalconfig/sa8155_adp/sa8155_adp_common/config/spi_props_8996.xml
<device id=DALDEVICEID_SPI_DEV_1>
<props name="SPI_ENABLED" type=DALPROP_ATTR_TYPE_UINT32> 1 </props>
- <props name="SW_ENABLE_BAM" type=DALPROP_ATTR_TYPE_UINT32> 0 </props>
+ <props name="SW_ENABLE_BAM" type=DALPROP_ATTR_TYPE_UINT32> 1 </props>
<props name="SW_USE_POLLING_MODE" type=DALPROP_ATTR_TYPE_UINT32> 0 </props>
<props name="SLAVE_MODE_ENABLE" type=DALPROP_ATTR_TYPE_UINT32> 0 </props>
<props name="SLAVE_DIRECT_WIRED" type=DALPROP_ATTR_TYPE_UINT32> 0 </props>
/* board specific settings Dirana primary MHz */
<props name="slave1 name" type=DALPROP_ATTR_TYPE_STRING_PTR>spiqup1_slave1_name</props>
<props name="slave1 mode" type=DALPROP_ATTR_TYPE_UINT32>0x2608</props>
<props name="slave1 clock" type=DALPROP_ATTR_TYPE_UINT32>5000000</props>
<props name="CLOCK_MASTER_NAME" type=DALPROP_ATTR_TYPE_STRING_PTR>scc_qupv3_wrap0_master_clock_name</props>
<props name="CLOCK_CORE_NAME" type=DALPROP_ATTR_TYPE_STRING_PTR>scc_qupv3_wrap0_core_clock_name</props>
<props name="CLOCK_GSI_NAME" type=DALPROP_ATTR_TYPE_STRING_PTR>scc_qupv3_wrap0_gsi_sequencer_clock_name</props>
<props name="CLOCK_SE_NAME" type=DALPROP_ATTR_TYPE_STRING_PTR>scc_qupv3_wrap0_serial_engine_2_clock_name</props>
<props name="CHIP_BLOCK_OFFSET" type=DALPROP_ATTR_TYPE_UINT32> 0 </props>
<props name="QUP_BLOCK_SIZE" type=DALPROP_ATTR_TYPE_UINT32> 0x2000 </props>
<props name="CHIP_PERIPH_SS_BASE" type=DALPROP_ATTR_TYPE_UINT32> 0x2688000 </props>
<props name="QUP_QGIC_IRQ" type=DALPROP_ATTR_TYPE_UINT32> 476 </props>
<props name="QUP_BASE_FREQ_KHZ" type=DALPROP_ATTR_TYPE_UINT32> 100000 </props>
</device>2. change the QUPAC_Access.c, download the corresponding TZ code accroding to the meta, and enter trustzone_images/core/settings/buses/qup_accesscontrol/qupv3/config/855/QUPAC_Access.c(Note: Talos=6150, Hana=855, Poipu=1000, Makena=Makena)
modify the QUP SE mode in const QUPv3_se_security_permissions_type qupv3_perms_auto[]
struct & const QUPv3_se_security_permissions_type ssc_qupv3_perms_auto[] struct
- { QUPV3_SSC_SE2, QUPV3_PROTOCOL_SPI, QUPV3_MODE_FIFO, AC_HLOS, TRUE, TRUE, FALSE },
+ { QUPV3_SSC_SE2, QUPV3_PROTOCOL_SPI, QUPV3_MODE_CPU_DMA, AC_HLOS, TRUE, TRUE, FALSE },
compiler the tz
cd trustzone_images/build/ms
python build_all.py -b TZ.XF.5.0 CHIPSET=sm8150 config=build_config_deploy.xml --recompileflash the devcfg
cd trustzone_images/build/ms/bin/YAQAANAA/
fastboot flash devcfg devcfg_auto.mbn3. change the qnx_ap/target/hypervisor/host/qcpe_config/8155/QCPE_config.xml.tmpl
<context_bank id="10" valid="TRUE" nestedToCB="68" dma_domain="VM_DMA1" type="NESTED" secure="FALSE">
<sid id="SID_MASK_QUP0_VM_RESERVED_0" owner="HOST" />
<sid id="SID_MASK_QUP1_VM_RESERVED_0" owner="HOST" />
<sid id="SID_MASK_QUP2_VM_RESERVED_0" owner="HOST" />
+ <sid id="SID_MASK_QUP0_SE" owner="HOST"/>
+ <sid id="SID_MASK_QUP1_SE" owner="HOST"/>
+ <sid id="SID_MASK_QUP2_SE" owner="HOST"/>
+ <sid id="SID_MASK_SSC_QUP_SE" owner="HOST" />
<!-- The following shall be removed once QUP Virtualization SMRs are fully integrated. -->
<sid id="SID_MASK_QUP0_AUDIO" owner="HOST" />
<sid id="SID_MASK_QUP1_AUDIO" owner="HOST" />
<sid id="SID_MASK_QUP2_AUDIO" owner="HOST" />
</context_bank>
<context_bank id="57" valid="TRUE" nestedToCB=S2_CB_NUM dma_domain=PVM_DOMAIN type="NESTED" secure="FALSE">
<sid id="SID_MASK_QUP0_VM_RESERVED_1" owner=PVM_VMID />
<!-- The following shall be removed once QUP Virtualization SMRs are fully integrated. -->
<!-- <sid id="SID_MASK_QUP0_SE" owner=PVM_VMID /> -->
</context_bank>
<context_bank id="58" valid="TRUE" nestedToCB=S2_CB_NUM dma_domain=PVM_DOMAIN type="NESTED" secure="FALSE">
<sid id="SID_MASK_QUP1_VM_RESERVED_1" owner=PVM_VMID />
<!-- The following shall be removed once QUP Virtualization SMRs are fully integrated. -->
<!-- <sid id="SID_MASK_QUP1_SE" owner=PVM_VMID /> -->
</context_bank>
<context_bank id="59" valid="TRUE" nestedToCB=S2_CB_NUM dma_domain=PVM_DOMAIN type="NESTED" secure="FALSE">
<sid id="SID_MASK_QUP2_VM_RESERVED_1" owner=PVM_VMID />
<!-- The following shall be removed once QUP Virtualization SMRs are fully integrated. -->
<!-- <sid id="SID_MASK_QUP2_SE" owner=PVM_VMID /> -->
</context_bank>
<context_bank id="60" valid="TRUE" nestedToCB=S2_CB_NUM dma_domain=PVM_DOMAIN type="NESTED" secure="FALSE">
<sid id="SID_MASK_SSC_QUP_VM_RESERVED_1" owner=PVM_VMID />
<!-- The following shall be removed once QUP Virtualization SMRs are fully integrated. -->
<!-- <sid id="SID_MASK_SSC_QUP_SE" owner=PVM_VMID /> -->
</context_bank>4. change the qnx_ap/AMSS/platform/hwdrivers/smmu_target_config/src/smmu_config_8150v2.c
/* {
0, //device entry
TRUE, //Deffered create
0xFFFF, //context bank id
"HLOS_WLAN", //remark
0xFFFF, //context bank number
{0x80010640}, //SID {0} attached to context bank
0xFFFF, //irq number
SMMU_HLOS_VMID, //HLOS access allowed
0, //context bank info
0, //enable PF
0, //set PF length
0, //TTRB0 for dump parser
0, //TTRB1 for dump parser
}, */
{
0, //device entry
TRUE, //Deffered create
0xFFFF, //context bank id
"HLOS_QUP_SE", //remark
0xFFFF, //context bank number
{0x800000C3,0x80000603,
0x800007A3,0x800004E3}, //SID {0} attached to context bank
0xFFFF, //irq number
SMMU_HLOS_VMID, //HLOS access allowed
0, //context bank info
0, //enable PF
0, //set PF length
},
3950
被折叠的 条评论
为什么被折叠?
到【灌水乐园】发言
