1.What is the STA Environment
实际就是指定约束,只有这个约束建立的正确、精确,这样才能去指导静态时序分析,对Design做一个正确的检查,这样才能确定建立时间和保持时间是否满足需求。若给一个不太准确的约束,那么做STA的时候,有可能结果不对。建立环境需要的东西:时钟建立好,IO的约束指定好,还有关于时序路径的一些特殊的约束。
Specification of correct constraints is important in analyzing STA results
The design environment should be specified accurately so that STA analysis can identify all the timing issues in the design
Preparing for STA involves amongst others,setting up clocks,specifying IO timing characteristics,and specifying false paths and multicycle paths。
STA针对的是同步电路,对异步电路是无能为力的。
2.Spacifying Clocks
要定义时钟,通常需要定义以下四个内容:
(1)clock source:it can be a port of the design,or be a pin of a cell inside the design(typically that is part of a clock generation logic)
(2)period:the time period of the clock
(3)Duty cycle(占空比):the high duration(positive phase)and the low duration(negative phase)
(4)Edge times:the time for the rising edge and the falling edge。就是指边沿翻转的时间
这样就可以写出如下的约束条件:
create_clock -name SYSCLK -period 20 -waveform {0 5} [get_ports 2 SCLK]
更多例子:
create_clock -period 5 [get_ports SCAN_CLK]
create_clock -name BDYCLK -period 15 -waveform {5 12} [get_ports GBLCLK]
可以通过set_clock_uncertainty对时钟的误差进行估计。定义clock_uncertainty后,时钟就会变得更加严苛,也就是说在检查建立时间和保持时间的时候条件会变得更悲观。实际上是对有效时钟周期的减小,通过这些悲观的设计可以让时序变得更加稳健。如果在定义了clock_uncertainty后时序依然满足条件,那么电路的安全性和稳健性将会变得很高。
The timing uncertainty of a clock period can be specified using the set_clock_uncertainty specification
The uncertainty can be used to model various factors that can