core-v-verif系列之lib＜47＞

UVM环境介绍
HEAD commitID： 1f968ef

1. core-v-verif/lib/uvm_agents/uvma_core_cntrl/uvma_core_cntrl_constants.sv

// Copyright 2020 OpenHW Group
// Copyright 2020 Datum Technology Corporation
// Copyright 2020 Silicon Labs, Inc.
//
// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
//     https://solderpad.org/licenses/
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.


`ifndef __UVMA_CORE_CNTRL_CONSTANTS_SV__
`define __UVMA_CORE_CNTRL_CONSTANTS_SV__

localparam CSR_ADDR_WL = 12;
localparam CSR_MASK_WL = (1 << CSR_ADDR_WL);

localparam MAX_XLEN   = 128;

localparam MAX_NUM_MHPMCOUNTERS = 29;
localparam MAX_NUM_HPMCOUNTERS  = 29;

`endif // __UVMA_CORE_CNTRL_CONSTANTS_SV__

2. 接口介绍

2.1 常量定义

localparam CSR_ADDR_WL = 12;
localparam CSR_MASK_WL = (1 << CSR_ADDR_WL);

• 代码介绍：定义了两个局部参数：
  • CSR_ADDR_WL：CSR地址宽度，设置为12位
  • CSR_MASK_WL：CSR掩码宽度，通过左移运算计算得出
• 逻辑分析：这些参数用于控制CSR（控制和状态寄存器）的地址空间大小，12位地址宽度可支持4096个不同的CSR地址。

2.2 位宽定义

localparam MAX_XLEN = 128;

• 代码介绍：定义了最大位宽为128位
• 逻辑分析：该参数限定了RISC-V架构支持的最大数据位宽，确保验证环境可以处理不同位宽（32/64/128位）的配置。

2.3 性能计数器定义

localparam MAX_NUM_MHPMCOUNTERS = 29;
localparam MAX_NUM_HPMCOUNTERS = 29;

• 代码介绍：定义了两个性能计数器参数：
  • MAX_NUM_MHPMCOUNTERS：机器模式性能计数器最大数量
  • MAX_NUM_HPMCOUNTERS：硬件性能计数器最大数量
• 逻辑分析：这些参数限定了RISC-V处理器中性能监控单元(PMU)支持的最大计数器数量，29个是RISC-V标准定义的典型值。

3. 参数介绍

3.1 头文件保护

`ifndef __UVMA_CORE_CNTRL_CONSTANTS_SV__
`define __UVMA_CORE_CNTRL_CONSTANTS_SV__
// ... 常量定义 ...
`endif // __UVMA_CORE_CNTRL_CONSTANTS_SV__

• 代码介绍：使用条件编译指令防止头文件重复包含
• 逻辑分析：这是SystemVerilog中标准的头文件保护机制，确保常量定义只被编译一次。

4. 模块实现介绍

4.1 常量值选择

• 代码介绍：所有常量值都采用RISC-V标准定义的典型值
• 逻辑分析：这些值经过精心选择，既满足RISC-V规范要求，又为验证环境提供了足够的灵活性。

5. 总结

该常量定义文件为RISC-V核心控制验证环境提供了：

1. 标准化的CSR地址空间定义
2. 支持不同位宽的配置能力
3. 性能监控单元的基础参数
4. 完善的编译保护机制

这些常量被设计为：

• 符合RISC-V规范要求
• 支持验证环境的灵活配置
• 通过头文件保护确保编译安全
• 为验证组件提供统一的参数基准

该文件是验证环境基础设施的重要组成部分，为整个验证平台提供了基础参数支持。

2. core-v-verif/lib/uvm_agents/uvma_core_cntrl/uvma_core_cntrl_drv.sv

// 
// Copyright 2020 OpenHW Group
// Copyright 2020 Datum Technology Corporation
// Copyright 2020 Silicon Labs, Inc.
//
// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// 
//     https://solderpad.org/licenses/
// 
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
// 

`ifndef __UVMA_CORE_CNTRL_DRV_SV__
`define __UVMA_CORE_CNTRL_DRV_SV__

/**
 * Component driving a Clock & Reset virtual interface (uvma_core_cntrl_if).
 */
class uvma_core_cntrl_drv_c extends uvm_driver;

   // Objects
   uvma_core_cntrl_cfg_c    cfg;
   uvma_core_cntrl_cntxt_c  cntxt;   

   `uvm_component_utils_begin(uvma_core_cntrl_drv_c)
      `uvm_field_object(cfg  , UVM_DEFAULT)
      `uvm_field_object(cntxt, UVM_DEFAULT)
   `uvm_component_utils_end
   
   /**
    * Default constructor.
    */
   extern function new(string name="uvma_core_cntrl_drv", uvm_component parent=null);
   
   /**
    * 1. Ensures cfg & cntxt handles are not null.
    * 2. Builds ap.
    */
   extern virtual function void build_phase(uvm_phase phase);

   /**
    * Initialize signals
    */
   extern virtual task reset_phase(uvm_phase phase);

   /**
    * Obtains the reqs from the sequence item port and calls drv_req()
    */
   extern virtual task run_phase(uvm_phase phase);

   /** 
    * Drive bootstrap pins    
    */
   extern virtual task drive_bootstrap();

endclass : uvma_core_cntrl_drv_c

function uvma_core_cntrl_drv_c::new(string name="uvma_core_cntrl_drv", uvm_component parent=null);
   
   super.new(name, parent);
   
endfunction : new

function void uvma_core_cntrl_drv_c::build_phase(uvm_phase phase);
   
   super.build_phase(phase);
   
   void'(uvm_config_db#(uvma_core_cntrl_cfg_c)::get(this, "", "cfg", cfg));
   if (!cfg) begin
      `uvm_fatal("CFG", "Configuration handle is null")
   end
   uvm_config_db#(uvma_core_cntrl_cfg_c)::set(this, "*", "cfg", cfg);
   
   void'(uvm_config_db#(uvma_core_cntrl_cntxt_c)::get(this, "", "cntxt", cntxt));
   if (!cntxt) begin
      `uvm_fatal("CNTXT", "Context handle is null")
   end
   uvm_config_db#(uvma_core_cntrl_cntxt_c)::set(this, "*", "cntxt", cntxt);
   
endfunction : build_phase

task uvma_core_cntrl_drv_c::reset_phase(uvm_phase phase);

   super.reset_phase(phase);

   drive_bootstrap();

endtask <