UVM环境介绍
HEAD commitID： 1f968ef
//
// Copyright 2021 OpenHW Group
// Copyright 2021 Datum Technology Corporation
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the "License"); you may
// not use this file except in compliance with the License, or, at your option,
// the Apache License version 2.0. You may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
// License for the specific language governing permissions and limitations
// under the License.
//
`ifndef __UVMA_OBI_MEMORY_IF_SV__
`define __UVMA_OBI_MEMORY_IF_SV__
/**
* Encapsulates all signals and clocking of Open Bus Interface interface. Used
* by monitor (uvma_obi_mon_c) and driver (uvma_obi_drv_c).
*/
interface uvma_obi_memory_if #(
parameter AUSER_WIDTH = `UVMA_OBI_MEMORY_AUSER_DEFAULT_WIDTH, ///< Width of the auser signal. RI5CY, Ibex, CV32E40* do not have the auser signal.
parameter WUSER_WIDTH = `UVMA_OBI_MEMORY_WUSER_DEFAULT_WIDTH, ///< Width of the wuser signal. RI5CY, Ibex, CV32E40* do not have the wuser signal.
parameter RUSER_WIDTH = `UVMA_OBI_MEMORY_RUSER_DEFAULT_WIDTH, ///< Width of the ruser signal. RI5CY, Ibex, CV32E40* do not have the ruser signal.
parameter ADDR_WIDTH = `UVMA_OBI_MEMORY_ADDR_DEFAULT_WIDTH , ///< Width of the addr signal.
parameter DATA_WIDTH = `UVMA_OBI_MEMORY_DATA_DEFAULT_WIDTH , ///< Width of the rdata and wdata signals. be width is DATA_WIDTH / 8. Valid DATA_WIDTH settings are 32 and 64.
parameter ID_WIDTH = `UVMA_OBI_MEMORY_ID_DEFAULT_WIDTH , ///< Width of the aid and rid signals.
parameter ACHK_WIDTH = `UVMA_OBI_MEMORY_ACHK_DEFAULT_WIDTH , ///< Width of the achk signal.
parameter RCHK_WIDTH = `UVMA_OBI_MEMORY_RCHK_DEFAULT_WIDTH ///< Width of the rchk signal.
)
(
input logic clk , ///< The bus clock times all bus transfers. All signal timings are related to the rising edge of clk.
input logic reset_n ///< The bus reset signal is active LOW and resets the system and the bus. This is the only active LOW signal.
);
// 'A Channel' signals
wire req ; ///< Address transfer request. req=1 signals the availability of valid address phase signals.
wire gnt ; ///< Grant. Ready to accept address transfer. Address transfer is accepted on rising clk with req=1 and gnt=1.
wire [(ADDR_WIDTH-1):0] addr ; ///< Address
wire we ; ///< Write Enable, high for writes, low for reads.
wire [((DATA_WIDTH/8)-1):0] be ; ///< Byte Enable. Is set for the bytes to write/read.
wire [(DATA_WIDTH-1):0] wdata ; ///< Write data. Only valid for write transactions. Undefined for read transactions.
wire [(AUSER_WIDTH-1):0] auser ; ///< Address Phase User signals. Valid for both read and write transactions.
wire [(WUSER_WIDTH-1):0] wuser ; ///< Additional Address Phase User signals. Only valid for write transactions. Undefined for read transactions.
wire [(ID_WIDTH-1):0] aid ; ///< Address Phase transaction identifier.
wire [5:0] atop ; ///< Atomic Operation.
wire [1:0] memtype; ///< Memory type attributes.
wire [2:0] prot ; ///< Protection attributes.
wire reqpar ; ///< Parity bit for req signal (odd parity).
wire gntpar ; ///< Parity bit for gnt signal (odd parity).
wire [(ACHK_WIDTH-1):0] achk ; ///< Checksum for address phase signals (except achk itself).
// 'R Channel' signals
wire rvalid ; ///< Response transfer request. rvalid=1 signals the availability of valid response phase signals. Used for both reads and writes.
wire rready ; ///< Ready to accept response transfer. Response transfer is accepted on rising clk with rvalid=1 and rready=1.
wire [(DATA_WIDTH-1):0] rdata ; ///< Read data. Only valid for read transactions. Undefined for write transactions.
wire err ; ///< Error.
wire [(RUSER_WIDTH-1):0] ruser ; ///< Response phase User signals. Only valid for read transactions. Undefined for write transactions.
wire [(ID_WIDTH-1):0] rid ; ///< Response Phase transaction identifier.
wire exokay ; ///< Exclusive transaction okay.
wire rvalidpar; ///< Parity bit for rvalid signal (odd parity).
wire rreadypar; ///< Parity bit for rready signal (odd parity).
wire [(RCHK_WIDTH-1):0] rchk ; ///< Checksum for address phase signals (except rchk itself).
/**
* Used by DUT in 'mstr' mode.
*/
clocking dut_mstr_cb @(posedge clk or reset_n);
input gnt ,
gntpar ,
rvalid ,
rdata ,
err ,
ruser ,
rid ,
exokay ,
rvalidpar,
rchk ;
output req ,
addr ,
we ,
be ,
wdata ,
auser ,
wuser ,
aid ,
atop ,
memtype ,
prot ,
reqpar ,
achk ,
rready ,
rreadypar;
endclocking : dut_mstr_cb
/**
* Used by DUT in 'slv' mode.
*/
clocking dut_slv_cb @(posedge clk or reset_n);
input req ,
addr ,
we ,
be ,
wdata ,
auser ,
wuser ,
aid ,
atop ,
memtype ,
prot ,
reqpar ,
achk ,
rready ,
rreadypar;
output gnt ,
gntpar ,
rvalid ,
rdata ,
err ,
ruser ,
rid ,
exokay ,
rvalidpar,
rchk ;
endclocking : dut_slv_cb
/**
* Used by uvma_obi_memory_drv_c.
*/
clocking drv_mstr_cb @(posedge clk or reset_n);
input gnt ,
gntpar ,
rvalid ,
rdata ,
err ,
ruser ,
rid ,
exokay ,
rvalidpar,
rchk ;
output req ,
addr ,
we ,
be ,
wdata ,
auser ,
wuser ,
aid ,
atop ,
memtype ,
prot ,
reqpar ,
achk ,
rready ,
rreadypar;
endclocking : drv_mstr_cb
/**
* Used by uvma_obi_memory_drv_c.
*/
clocking drv_slv_cb @(posedge clk or reset_n);
input req ,
addr ,
we ,
be ,
wdata ,
auser ,
wuser ,
aid ,
atop ,
memtype ,
prot ,
reqpar ,
achk ,
rready ,
rreadypar;
inout gnt ;
output gntpar ,
rvalid ,
rdata ,
err ,
ruser ,
rid ,
exokay ,
rvalidpar,
rchk ;
endclocking : drv_slv_cb
/**
* Used by uvma_obi_memory_mon_c.
*/
clocking mon_cb @(posedge clk or reset_n);
input req ,
gnt ,
addr ,
we ,
be ,
wdata ,
auser ,
wuser ,
aid ,
atop ,
memtype ,
prot ,
reqpar ,
gntpar ,
achk ,
rvalid ,
rready ,
rdata ,
err ,
ruser ,
rid ,
exokay ,
rvalidpar,
rreadypar,
rchk ;
endclocking : mon_cb
modport dut_mstr_mp (clocking dut_mstr_cb); ///< Used by DUT in 'mstr' mode.
modport dut_slv_mp (clocking dut_slv_cb ); ///< Used by DUT in 'slv' mode.
modport active_mstr_mp(clocking drv_mstr_cb); ///< Used by uvma_obi_drv_c in 'mstr' mode.
modport active_slv_mp (clocking drv_slv_cb ); ///< Used by uvma_obi_drv_c in 'slv' mode.
modport passive_mp (clocking mon_cb ); ///< Used by uvma_obi_mon_c.
endinterface : uvma_obi_memory_if
`endif // __UVMA_OBI_MEMORY_IF_SV__
lib/uvm_agents/uvma_obi_memory/src/uvma_obi_memory_if.sv
1. 简要介绍
该文件是OBI内存接口的SystemVerilog接口定义，主要功能包括：
- 定义OBI协议1.2版本的所有信号
- 提供主从设备的不同时钟域视图
- 支持参数化配置总线位宽
- 实现驱动和监控的时钟块定义
2. 接口介绍
2.1 接口定义
interface uvma_obi_memory_if #(
parameter AUSER_WIDTH = `UVMA_OBI_MEMORY_AUSER_DEFAULT_WIDTH
)
- 代码介绍：参数化接口定义
- 特点：支持多种位宽配置
2.2 时钟块定义
clocking dut_mstr_cb @(posedge clk or reset_n);
input gnt;
output req;
endclocking
- 代码介绍：定义DUT主模式时钟块
- 功能：提供主设备时序视图
3. 参数介绍
3.1 位宽参数
parameter ADDR_WIDTH = `UVMA_OBI_MEMORY_ADDR_DEFAULT_WIDTH
- 参数说明：地址总线默认32位
- 用途：控制地址信号宽度
3.2 用户信号参数
parameter AUSER_WIDTH = `UVMA_OBI_MEMORY_AUSER_DEFAULT_WIDTH
- 参数说明：地址用户信号宽度
- 特点：支持可选的用户扩展信号
4. 模块实现介绍
4.1 信号定义
wire [(ADDR_WIDTH-1):0] addr;
wire [(DATA_WIDTH-1):0] wdata;
- 代码分析：
- 定义地址和数据总线
- 使用参数化位宽
- 支持32/64位数据宽度
4.2 模式端口定义
modport dut_mstr_mp(clocking dut_mstr_cb);
modport active_slv_mp(clocking drv_slv_cb);
- 代码分析：
- 定义DUT主模式接口
- 定义驱动从模式接口
- 提供不同的时序视图
5. 总结
该接口文件具有以下特点：
- 完整的OBI协议1.2支持
- 灵活的参数化配置
- 清晰的时钟域划分
- 标准化的modport定义
作为验证环境的核心组件，它为OBI内存接口提供了统一的硬件/软件视图，确保验证组件能够正确驱动和监控总线信号。
lib/uvm_agents/uvma_obi_memory/src/seq/
//
// Copyright 2021 OpenHW Group
// Copyright 2021 Datum Technology Corporation
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the "License"); you may
// not use this file except in compliance with the License, or, at your option,
// the Apache License version 2.0. You may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
// License for the specific language governing permissions and limitations
// under the License.
//
`ifndef __UVMA_OBI_MEMORY_BASE_SEQ_ITEM_SV__
`define __UVMA_OBI_MEMORY_BASE_SEQ_ITEM_SV__
/**
* Object created by Open Bus Interface agent sequences extending uvma_obi_memory_seq_base_c.
*/
class uvma_obi_memory_base_seq_item_c extends uvml_trn_seq_item_c;
// Data
rand uvma_obi_memory_access_type_enum access_type; ///< Read or write
// Metadata
uvma_obi_memory_cfg_c cfg; ///< Handle to agent's configuration object
`uvm_object_utils_begin(uvma_obi_memory_base_seq_item_c)
`uvm_field_enum(uvma_obi_memory_access_type_enum, access_type, UVM_DEFAULT)
`uvm_object_utils_end
/**
* Default constructor.
*/
extern function new(string name="uvma_obi_memory_base_seq_item");
endclass : uvma_obi_memory_base_seq_item_c
function uvma_obi_memory_base_seq_item_c::new(string name="uvma_obi_memory_base_seq_item");
super.new(name);
endfunction : new
`endif // __UVMA_OBI_MEMORY_BASE_SEQ_ITEM_SV__
uvma_obi_memory_base_seq_item.sv
1. 简要介绍
该文件是OBI内存接口的基础序列项类定义，主要功能包括：
- 定义OBI事务的基本数据结构
- 封装内存访问类型（读/写）
- 提供配置对象引用
- 作为所有OBI序列项的基类
2. 接口介绍
2.1 类定义
class uvma_obi_memory_base_seq_item_c extends uvml_trn_seq_item_c;
- 代码介绍：定义基础序列项类
- 继承关系：继承自uvml_trn_seq_item_c基类
- 功能：提供事务记录基础能力
3. 参数介绍
3.1 访问类型枚举
rand uvma_obi_memory_access_type_enum access_type;
- 参数说明：随机化内存访问类型
- 取值：READ或WRITE枚举值
- 特点：支持随机化测试场景
3.2 配置对象
uvma_obi_memory_cfg_c cfg;
- 参数说明：存储验证配置
- 用途：控制序列项行为
4. 模块实现介绍
4.1 UVM自动化注册
`uvm_object_utils_begin(uvma_obi_memory_base_seq_item_c)
`uvm_field_enum(uvma_obi_memory_access_type_enum, access_type, UVM_DEFAULT)
`uvm_object_utils_end
- 代码分析：
- 注册UVM对象
- 自动化字段操作
- 支持默认的copy/compare操作
4.2 构造函数
function new(string name="uvma_obi_memory_base_seq_item");
super.new(name);
endfunction
- 代码分析：
- 调用父类构造函数
- 设置默认实例名
- 简单的初始化逻辑
5. 总结
该基础序列项类具有以下特点：
- 标准化的UVM实现
- 灵活的内存访问控制
- 完善的配置支持
- 可扩展的设计架构
作为验证环境的基础组件，它为OBI内存接口测试序列提供了统一的事务模型，确保测试场景能够准确描述各类内存操作。
//
// Copyright 2021 Datum Technology Corporation
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the "License"); you may
// not use this file except in compliance with the License, or, at your option,
// the Apache License version 2.0. You may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
// License for the specific language governing permissions and limitations
// under the License.
//
`ifndef __UVMA_OBI_MEMORY_BASE_SEQ_SV__
`define __UVMA_OBI_MEMORY_BASE_SEQ_SV__
/**
* Abstract object from which all other Open Bus Interface agent
* sequences must extend. Subclasses must be run on Open Bus Interface
* sequencer (uvma_obi_sqr_c) instance.
*/
class uvma_obi_memory_base_seq_c extends uvm_sequence#(
.REQ(uvma_obi_memory_base_seq_item_c),
.RSP(uvma_obi_memory_mon_trn_c )
);
// Agent handles
uvma_obi_memory_cfg_c cfg;
uvma_obi_memory_cntxt_c cntxt;
`uvm_object_utils(uvma_obi_memory_base_seq_c)
`uvm_declare_p_sequencer(uvma_obi_memory_sqr_c)
/**
* Default constructor.
*/
extern function new(string name="uvma_obi_memory_base_seq");
/**
* Assigns cfg and cntxt handles from p_sequencer.
*/
extern virtual task pre_start();
endclass : uvma_obi_memory_base_seq_c
function uvma_obi_memory_base_seq_c::new(string name="uvma_obi_memory_base_seq");
super.new(name);
endfunction : new
task uvma_obi_memory_base_seq_c::pre_start();
cfg = p_sequencer.cfg;
cntxt = p_sequencer.cntxt;
endtask : pre_start
`endif // __UVMA_OBI_MEMORY_BASE_SEQ_SV__
uvma_obi_memory_base_seq.sv
1. 简要介绍
该文件是OBI内存接口的基础序列类定义，主要功能包括：
- 作为所有OBI序列的基类
- 提供配置和上下文对象访问
- 定义标准序列接口
- 支持事务和监控响应
2. 接口介绍
2.1 类定义
class uvma_obi_memory_base_seq_c extends uvm_sequence#(
.REQ(uvma_obi_memory_base_seq_item_c),
.RSP(uvma_obi_memory_mon_trn_c)
);
- 代码介绍：定义参数化序列基类
- 模板参数：
- REQ：请求事务类型
- RSP：响应事务类型
3. 参数介绍
3.1 配置对象
uvma_obi_memory_cfg_c cfg;
- 参数说明：存储验证配置
- 用途：控制序列行为
3.2 上下文对象
uvma_obi_memory_cntxt_c cntxt;
- 参数说明：存储运行时状态
- 包含内容：接口实例和事件触发器
4. 模块实现介绍
4.1 UVM自动化注册
`uvm_object_utils(uvma_obi_memory_base_seq_c)
`uvm_declare_p_sequencer(uvma_obi_memory_sqr_c)
- 代码分析：
- 注册UVM对象
- 声明序列器指针
- 支持自动化操作
4.2 预启动任务
task pre_start();
cfg = p_sequencer.cfg;
cntxt = p_sequencer.cntxt;
endtask
- 代码分析：
- 从序列器获取配置和上下文
- 在序列启动前执行
- 确保序列运行时环境就绪
5. 总结
该基础序列类具有以下特点：
- 标准的UVM实现架构
- 灵活的配置管理
- 完善的运行时环境支持
- 可扩展的设计模式
作为验证环境的核心组件，它为OBI内存接口测试序列提供了统一的开发框架，确保测试场景能够正确访问验证环境和配置参数。
//
// Copyright 2021 OpenHW Group
// Copyright 2021 Datum Technology Corporation
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the "License"); you may
// not use this file except in compliance with the License, or, at your option,
// the Apache License version 2.0. You may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
// License for the specific language governing permissions and limitations
// under the License.
//
`ifndef __UVMA_OBI_MEMORY_FW_PRELOAD_SEQ_SV__
`define __UVMA_OBI_MEMORY_FW_PRELOAD_SEQ_SV__
/**
* Virtual sequence implementing the cv32e40x virtual peripherals.
* TODO Move most of the functionality to a cv32e env base class.
*/
class uvma_obi_memory_fw_preload_seq_c extends uvma_obi_memory_base_seq_c;
string fw_file_path;
`uvm_object_utils_begin(uvma_obi_memory_fw_preload_seq_c)
`uvm_object_utils_end
/**
* Default constructor.
*/
extern function new(string name="uvma_obi_memory_fw_preload_seq");
/**
* Implement the sequence using plusarg to load a firmware file
*/
extern virtual task body();
endclass : uvma_obi_memory_fw_preload_seq_c
function uvma_obi_memory_fw_preload_seq_c::new(string name="uvma_obi_memory_fw_preload_seq");
super.new(name);
endfunction : new
task uvma_obi_memory_fw_preload_seq_c::body();
if ($value$plusargs("firmware=%s", fw_file_path)) begin
cntxt.mem.readmemh(fw_file_path);
end
endtask : body
`endif // __UVMA_OBI_MEMORY_FW_PRELOAD_SEQ_SV__
uvma_obi_memory_fw_preload_seq.sv
1. 简要介绍
该文件是OBI内存接口的固件预加载序列实现，主要功能包括：
- 实现固件文件预加载功能
- 通过命令行参数获取固件路径
- 将固件内容加载到内存模型
- 作为虚拟外设的基础功能
2. 接口介绍
2.1 类定义
class uvma_obi_memory_fw_preload_seq_c extends uvma_obi_memory_base_seq_c;
- 代码介绍：定义固件预加载序列类
- 继承关系：继承自OBI基础序列类
- 特点：支持固件文件加载
3. 参数介绍
3.1 固件文件路径
string fw_file_path;
- 参数说明：存储固件文件路径
- 来源：通过命令行参数获取
4. 模块实现介绍
4.1 UVM自动化注册
`uvm_object_utils_begin(uvma_obi_memory_fw_preload_seq_c)
`uvm_object_utils_end
- 代码分析：
- 注册UVM对象
- 支持自动化操作
- 无额外字段需要注册
4.2 主体任务实现
task body();
if ($value$plusargs("firmware=%s", fw_file_path)) begin
cntxt.mem.readmemh(fw_file_path);
end
endtask
- 代码分析：
- 通过plusarg获取固件路径
- 调用内存模型的readmemh方法
- 将固件内容加载到内存
5. 总结
该固件预加载序列具有以下特点：
- 简洁的命令行接口
- 标准的内存加载方式
- 灵活的固件支持
- 可扩展的设计架构
作为验证环境的基础组件，它为处理器验证提供了便捷的固件加载能力，确保测试场景能够快速初始化内存内容。
//
// Copyright 2021 OpenHW Group
// Copyright 2021 Datum Technology Corporation
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the "License"); you may
// not use this file except in compliance with the License, or, at your option,
// the Apache License version 2.0. You may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
// License for the specific language governing permissions and limitations
// under the License.
//
`ifndef __UVMA_OBI_MEMORY_MSTR_BASE_SEQ_SV__
`define __UVMA_OBI_MEMORY_MSTR_BASE_SEQ_SV__
/**
* TODO Describe uvma_obi_memory_mstr_base_seq_c
*/
class uvma_obi_memory_mstr_base_seq_c extends uvma_obi_memory_base_seq_c;
// Fields
`uvm_object_utils_begin(uvma_obi_memory_mstr_base_seq_c)
`uvm_object_utils_end
/**
* Default constructor.
*/
extern function new(string name="uvma_obi_memory_mstr_base_seq");
/**
* TODO Describe uvma_obi_memory_mstr_base_seq_c::body()
*/
extern virtual task body();
endclass : uvma_obi_memory_mstr_base_seq_c
function uvma_obi_memory_mstr_base_seq_c::new(string name="uvma_obi_memory_mstr_base_seq");
super.new(name);
endfunction : new
task uvma_obi_memory_mstr_base_seq_c::body();
// TODO Implement uvma_obi_memory_mstr_base_seq_c::body()
endtask : body
`endif // __UVMA_OBI_MEMORY_MSTR_BASE_SEQ_SV__
uvma_obi_memory_mstr_base_seq.sv
1. 简要介绍
该文件是OBI内存接口主模式基础序列类定义，主要功能包括：
- 作为主模式测试序列的基类
- 提供标准序列接口
- 支持事务生成和响应处理
- 预留基础框架供具体序列实现
2. 接口介绍
2.1 类定义
class uvma_obi_memory_mstr_base_seq_c extends uvma_obi_memory_base_seq_c;
- 代码介绍：定义主模式基础序列类
- 继承关系：继承自OBI基础序列类
- 特点：专为主模式测试场景设计
3. 参数介绍
3.1 UVM自动化注册
`uvm_object_utils_begin(uvma_obi_memory_mstr_base_seq_c)
`uvm_object_utils_end
- 参数说明：空字段注册
- 用途：保持UVM对象标准操作
4. 模块实现介绍
4.1 构造函数
function new(string name="uvma_obi_memory_mstr_base_seq");
super.new(name);
endfunction
- 代码分析：
- 调用父类构造函数
- 设置默认实例名
- 简单初始化逻辑
4.2 主体任务
task body();
// TODO Implement uvma_obi_memory_mstr_base_seq_c::body()
endtask
- 代码分析：
- 预留实现空壳
- 需要子类具体实现
- 标记为待完成状态
5. 总结
该主模式基础序列类具有以下特点：
- 标准化的UVM实现架构
- 清晰的继承关系
- 灵活的可扩展性
- 明确的实现要求
作为验证环境的基础组件，它为OBI主模式测试序列提供了统一的开发框架，确保主设备测试场景能够基于标准接口实现。
//
// Copyright 2021 OpenHW Group
// Copyright 2021 Datum Technology Corporation
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the "License"); you may
// not use this file except in compliance with the License, or, at your option,
// the Apache License version 2.0. You may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
// License for the specific language governing permissions and limitations
// under the License.
//
`ifndef __UVMA_OBI_MEMORY_MSTR_SEQ_ITEM_SV__
`define __UVMA_OBI_MEMORY_MSTR_SEQ_ITEM_SV__
/**
* Object created by Open Bus Interface agent sequences extending
* uvma_obi_mstr_seq_base_c.
*/
class uvma_obi_memory_mstr_seq_item_c extends uvma_obi_memory_base_seq_item_c;
// Data
rand uvma_obi_memory_addr_b_t address; ///< Read/Write Address
rand uvma_obi_memory_data_b_t wdata ; ///< Write Data
uvma_obi_memory_data_b_t rdata ; ///< Read Data
rand uvma_obi_memory_be_b_t be ; ///< Byte Enable. Is set for the bytes to write/read.
rand uvma_obi_memory_auser_b_t auser ; ///< Address Phase User signals. Valid for both read and write transactions.
rand uvma_obi_memory_wuser_b_t wuser ; ///< Additional Address Phase User signals. Only valid for write transactions.
rand uvma_obi_memory_ruser_b_t ruser ; ///< Response phase User signals. Only valid for read transactions. Undefined for write transactions.
rand uvma_obi_memory_id_b_t id ; ///< Address/Response Phase transaction identifier.
// Metadata
rand int unsigned req_latency ; ///< Number of cycles before req is asserted
rand int unsigned rready_latency; ///< Number of cycles before rready is asserted after rvalid has been asserted
rand int unsigned rready_hold ; ///< Number of cycles to keep rready asserted after rvalid has been de-asserted
rand int unsigned tail_length ; ///< Number of idle cycles after rready has been de-asserted
`uvm_object_utils_begin(uvma_obi_memory_mstr_seq_item_c)
`uvm_field_int ( address , UVM_DEFAULT )
`uvm_field_int ( wdata , UVM_DEFAULT )
`uvm_field_int ( rdata , UVM_DEFAULT )
`uvm_field_int ( be , UVM_DEFAULT + UVM_BIN)
`uvm_field_int ( auser , UVM_DEFAULT )
`uvm_field_int ( wuser , UVM_DEFAULT )
`uvm_field_int ( ruser , UVM_DEFAULT )
`uvm_field_int ( id , UVM_DEFAULT )
`uvm_field_int(req_latency , UVM_DEFAULT + UVM_DEC + UVM_NOCOMPARE)
`uvm_field_int(rready_latency, UVM_DEFAULT + UVM_DEC + UVM_NOCOMPARE)
`uvm_field_int(rready_hold , UVM_DEFAULT + UVM_DEC + UVM_NOCOMPARE)
`uvm_field_int(tail_length , UVM_DEFAULT + UVM_DEC + UVM_NOCOMPARE)
`uvm_object_utils_end
/**
* Describe defaults_cons
*/
constraint defaults_cons {
/*soft*/ id == __uid;
/*soft*/ req_latency == 0;
/*soft*/ rready_latency == 0;
/*soft*/ rready_hold == 1;
/*soft*/ tail_length == 1;
foreach (be[ii]) {
/*soft*/ be[ii] == 1'b1;
}
}
/**
* Describe rules_cons
*/
constraint rules_cons {
be != '0;
}
/**
* Default constructor.
*/
extern function new(string name="uvma_obi_memory_mstr_seq_item");
endclass : uvma_obi_memory_mstr_seq_item_c
function uvma_obi_memory_mstr_seq_item_c::new(string name="uvma_obi_memory_mstr_seq_item");
super.new(name);
endfunction : new
`endif // __UVMA_OBI_MEMORY_MSTR_SEQ_ITEM_SV__
uvma_obi_memory_mstr_seq_item.sv
1. 简要介绍
该文件是OBI内存接口主模式序列项类定义，主要功能包括：
- 定义主模式事务数据结构
- 封装地址、数据和控制信号
- 支持随机化测试场景
- 提供事务延迟控制
2. 接口介绍
2.1 类定义
class uvma_obi_memory_mstr_seq_item_c extends uvma_obi_memory_base_seq_item_c;
- 代码介绍：定义主模式序列项类
- 继承关系：继承自OBI基础序列项类
- 特点：扩展主模式特有字段
3. 参数介绍
3.1 地址数据字段
rand uvma_obi_memory_addr_b_t address;
rand uvma_obi_memory_data_b_t wdata;
uvma_obi_memory_data_b_t rdata;
- 参数说明：
- address：随机化访问地址
- wdata：随机化写入数据
- rdata：读取数据（非随机）
3.2 控制信号字段
rand uvma_obi_memory_be_b_t be;
rand uvma_obi_memory_auser_b_t auser;
- 参数说明：
- be：字节使能信号
- auser：地址用户信号
4. 模块实现介绍
4.1 UVM自动化注册
`uvm_object_utils_begin(uvma_obi_memory_mstr_seq_item_c)
`uvm_field_int(address, UVM_DEFAULT)
`uvm_field_int(wdata, UVM_DEFAULT)
`uvm_object_utils_end
- 代码分析：
- 注册所有关键字段
- 支持自动化操作
- 配置不同的显示格式
4.2 约束条件
constraint defaults_cons {
/*soft*/ id == __uid;
/*soft*/ req_latency == 0;
}
constraint rules_cons {
be != '0;
}
- 代码分析：
- 设置默认值约束
- 强制字节使能非零
- 支持约束重载
5. 总结
该主模式序列项类具有以下特点：
- 完整的事务字段定义
- 灵活的随机化控制
- 严格的协议约束
- 标准化的UVM实现
作为验证环境的核心组件，它为OBI主模式测试提供了统一的事务模型，确保测试场景能够准确描述各类内存操作。
//
// Copyright 2021 OpenHW Group
// Copyright 2021 Datum Technology Corporation
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the "License"); you may
// not use this file except in compliance with the License, or, at your option,
// the Apache License version 2.0. You may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
// License for the specific language governing permissions and limitations
// under the License.
//
`ifndef __UVMA_OBI_MEMORY_SLV_BASE_SEQ_SV__
`define __UVMA_OBI_MEMORY_SLV_BASE_SEQ_SV__
/**
* TODO Describe uvma_obi_memory_slv_base_seq_c
*/
class uvma_obi_memory_slv_base_seq_c extends uvma_obi_memory_base_seq_c;
// Fields
`uvm_object_utils_begin(uvma_obi_memory_slv_base_seq_c)
`uvm_object_utils_end
/**
* Default constructor.
*/
extern function new(string name="uvma_obi_memory_slv_base_seq");
/**
* TODO Describe uvma_obi_memory_slv_base_seq_c::body()
*/
extern task body();
/**
* TODO Describe uvma_obi_memory_slv_base_seq_c::do_response()
*/
extern virtual task do_response(ref uvma_obi_memory_mon_trn_c mon_req);
/**
* Convenience function to encapsulate the add_* reponse functions to generate all non-data response fields
*/
extern virtual function void add_r_fields(uvma_obi_memory_mon_trn_c mon_req, uvma_obi_memory_slv_seq_item_c slv_rsp);
/**
* Standard method to add a random ralid latency
*/
extern virtual function void add_latencies(uvma_obi_memory_slv_seq_item_c slv_rsp);
/**
* Standard method to add a random error response as based on cfg knobs
*/
extern virtual function void add_err(uvma_obi_memory_slv_seq_item_c slv_rsp);
/**
* Standard method to add a random exclusive okay response as based on cfg knobs
*/
extern virtual function void add_exokay(uvma_obi_memory_mon_trn_c mon_req, uvma_obi_memory_slv_seq_item_c slv_rsp);
/**
* Standard method to add a random or custom ruser, default implementation writes 0
*/
extern virtual function void add_rchk(uvma_obi_memory_slv_seq_item_c slv_rsp);
/**
* Standard method to add a random or custom rchk, default implementation writes 0
*/
extern virtual function void add_ruser(uvma_obi_memory_slv_seq_item_c slv_rsp);
endclass : uvma_obi_memory_slv_base_seq_c
function uvma_obi_memory_slv_base_seq_c::new(string name="uvma_obi_memory_slv_base_seq");
super.new(name);
endfunction : new
task uvma_obi_memory_slv_base_seq_c::body();
uvma_obi_memory_mon_trn_c mon_trn;
forever begin
// Wait for the monitor to send us the mstr's "req" with an access request
p_sequencer.mon_trn_fifo.get(mon_trn);
`uvm_info("OBI_MEMORY_SLV_SEQ", $sformatf("Got mon_trn:\n%s", mon_trn.sprint()), UVM_HIGH)
do_response(mon_trn);
end
endtask : body
task uvma_obi_memory_slv_base_seq_c::do_response(ref uvma_obi_memory_mon_trn_c mon_req);
`uvm_fatal("OBI_MEMORY_SLV_SEQ", "Call to pure virtual task")
endtask : do_response
function void uvma_obi_memory_slv_base_seq_c::add_latencies(uvma_obi_memory_slv_seq_item_c slv_rsp);
slv_rsp.rvalid_latency = cfg.calc_random_rvalid_latency();
endfunction : add_latencies
function void uvma_obi_memory_slv_base_seq_c::add_r_fields(uvma_obi_memory_mon_trn_c mon_req, uvma_obi_memory_slv_seq_item_c slv_rsp);
// This is just a convenience function
// Take care to leave rchk last as it will likely incorporate a checksum of all other response fields
slv_rsp.rid = mon_req.aid;
add_latencies(slv_rsp);
if (cfg.version >= UVMA_OBI_MEMORY_VERSION_1P2) begin
add_err(slv_rsp);
add_exokay(mon_req, slv_rsp);
add_ruser(slv_rsp);
add_rchk(slv_rsp);
end
endfunction : add_r_fields
function void uvma_obi_memory_slv_base_seq_c::add_err(uvma_obi_memory_slv_seq_item_c slv_rsp);
slv_rsp.err = cfg.calc_random_err(slv_rsp.orig_trn.address);
endfunction : add_err
function void uvma_obi_memory_slv_base_seq_c::add_exokay(uvma_obi_memory_mon_trn_c mon_req, uvma_obi_memory_slv_seq_item_c slv_rsp);
// Only respond exokay == 1 to SC or LR as signaled by atop
if (mon_req.atop[5] != 1'b1 || !(mon_req.atop[4:0] inside {5'h2, 5'h3})) begin
slv_rsp.exokay = 0;
return;
end
slv_rsp.exokay = cfg.calc_random_exokay(slv_rsp.orig_trn.address);
endfunction : add_exokay
function void uvma_obi_memory_slv_base_seq_c::add_ruser(uvma_obi_memory_slv_seq_item_c slv_rsp);
slv_rsp.ruser = '0;
endfunction : add_ruser
function void uvma_obi_memory_slv_base_seq_c::add_rchk(uvma_obi_memory_slv_seq_item_c slv_rsp);
// FIXME:need to implement this
// slv_rsp.rchk = '0;
endfunction : add_rchk
`endif // __UVMA_OBI_MEMORY_SLV_BASE_SEQ_SV__
uvma_obi_memory_slv_base_seq.sv
1. 简要介绍
该文件是OBI内存接口从模式基础序列类定义，主要功能包括：
- 作为从设备响应序列的基类
- 处理主设备请求并生成响应
- 支持随机延迟和错误注入
- 提供原子操作响应机制
2. 接口介绍
2.1 类定义
class uvma_obi_memory_slv_base_seq_c extends uvma_obi_memory_base_seq_c;
- 代码介绍：定义从模式基础序列类
- 继承关系：继承自OBI基础序列类
- 特点：专为从设备响应设计
3. 参数介绍
3.1 UVM自动化注册
`uvm_object_utils_begin(uvma_obi_memory_slv_base_seq_c)
`uvm_object_utils_end
- 参数说明：空字段注册
- 用途：保持UVM对象标准操作
4. 模块实现介绍
4.1 主体任务
task body();
forever begin
p_sequencer.mon_trn_fifo.get(mon_trn);
do_response(mon_trn);
end
endtask
- 代码分析：
- 持续监听监控事务
- 获取主设备请求
- 调用响应处理任务
4.2 响应字段处理
function void add_r_fields(uvma_obi_memory_mon_trn_c mon_req, uvma_obi_memory_slv_seq_item_c slv_rsp);
slv_rsp.rid = mon_req.aid;
add_latencies(slv_rsp);
add_err(slv_rsp);
endfunction
- 代码分析：
- 设置响应ID匹配请求ID
- 添加随机延迟
- 注入随机错误
5. 总结
该从模式基础序列类具有以下特点：
- 标准化的响应处理流程
- 灵活的延迟控制机制
- 完善的错误注入支持
- 可扩展的设计架构
作为验证环境的核心组件，它为OBI从模式测试提供了统一的响应框架，确保从设备能够正确响应各类主设备请求。
扫一扫
2152
被折叠的 条评论
为什么被折叠?
到【灌水乐园】发言
