组合电路的vhdl设计
2选1多路选择器
ENTITY mux21a IS
PORT(a,b,s:IN BIT;
y:OUT BIT);
END ENTITY mux21a;
ARCHITECTURE bhv OF mux21a IS
BEGIN
PROCESS(a,b,s)
BEGIN
IF(s='1') THEN y<=a;ELSE y<=b;
END IF;
END PROCESS;
END ARCHITECTURE bhv;
半加器
SO=A⊕B;CO=A·B
原创
2020-10-18 14:29:42 ·
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