开发环境:Vivado 2017.2
开发板:米联MZ702B
VHDL程序1:
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 2018/02/12 17:32:02
-- Design Name:
-- Module Name: led_water - Behavioral
-- Project Name:
-- Target Devices: MZ702B
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
--------------------------------------------------------------------------------------------------
entity VHDL_LEDWATER is
port(
CLK_i : in STD_LOGIC; --创建时钟端口,连接开发板PIN H16
RSTn_i : in STD_LOGIC; --创建复位端口,连接开发板PIN T19
LED_o : out BIT_VECTOR(3 downto 0) --创建输出端口,对应4个LED。分别
--为J16,K16,G15,H15,要使用移位操作符
); --其左侧必须为BIT_VECTOR类型
end VHDL_LEDWATER;
--------------------------------------------------------------------------------------------------
architecture behave of VHDL_LEDWATER is
signal Clk1 : STD_LOGIC; --建立中间时钟信号
begin
P1:process(CLK_i)
variable count : INTEGER range 0 to 50000000 := 0; --变量初始值不可综合,在仿真中使用,并
variable count1: STD_LOGIC := '1'; --且为便于仿真,这里取到25,当烧写到开
--发板时候,改写为50000000即可
variable temp : BIT_VECTOR(3 downto 0) := "0001"; --注意左操作数类型
begin
if(RSTn_i = '0') then
count := 0;
elsif(CLK_i'event and CLK_i = '1') then
count := count + 1;
if(count = 50000000) then --这里使用=,而不是>=,可以防止产生比较器,节省硬件资源
count := 0;
temp := (temp rol 1);
LED_o <= temp;
end if;
end if;
end process P1;
end architecture;
VHDL程序2:
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 2018/02/12 17:32:02
-- Design Name:
-- Module Name: led_water - Behavioral
-- Project Name:
-- Target Devices: MZ702B
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
--library IEEE;
--use IEEE.std_logic_1164.all;
--------------------------------------------------------------------------------------------------
entity VHDL_LEDWATER is
port(
CLK_i : in STD_LOGIC; --创建时钟端口,连接开发板PIN H16
RSTn_i : in STD_LOGIC; --创建复位端口,连接开发板PIN T19
LED_o : out BIT_VECTOR(3 downto 0) --创建输出端口,对应4个LED。分别
--为J16,K16,G15,H15,要使用移位操作符
); --其左侧必须为BIT_VECTOR类型
end VHDL_LEDWATER;
--------------------------------------------------------------------------------------------------
architecture behave of VHDL_LEDWATER is
signal Clk1 : STD_LOGIC; --建立中间时钟信号
begin
P1:process(CLK_i)
variable count : INTEGER range 0 to 50000000 := 0; --变量初始值不可综合,在仿真中使用,并
variable count1: STD_LOGIC := '1'; --且为便于仿真,这里取到25,当烧写到开
--发板时候,改写为50000000即可
begin
if(RSTn_i = '0') then
count := 0;
elsif(CLK_i'event and CLK_i = '1') then
count := count + 1;
if(count = 50000000) then --这里使用=,而不是>=,可以防止产生比较器,节省硬件资源
count := 0;
count1 := not count1;
end if;
end if;
Clk1 <= count1;
end process P1;
P2:process(Clk1)
variable temp : BIT_VECTOR(3 downto 0) := "0001"; --注意左操作数类型
begin
if(Clk1'event and Clk1 = '1') then
temp := (temp rol 1);
end if;
LED_o <= temp;
end process P2;
end architecture;
约束文件:
create_clock -period 10.000 -name CLK_i [get_ports CLK_i]
set_property PACKAGE_PIN H16 [get_ports CLK_i]
set_property IOSTANDARD LVCMOS33 [get_ports CLK_i]
set_property PACKAGE_PIN T19 [get_ports RSTn_i]
set_property IOSTANDARD LVCMOS33 [get_ports RSTn_i]
set_property PACKAGE_PIN J16 [get_ports {LED_o[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED_o[0]}]
set_property PACKAGE_PIN K16 [get_ports {LED_o[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED_o[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED_o[2]}]
set_property PACKAGE_PIN G15 [get_ports {LED_o[2]}]
set_property PACKAGE_PIN H15 [get_ports {LED_o[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED_o[3]}]