VHDL学习笔记——LED流水灯

最新推荐文章于 2022-09-23 22:34:41 发布

阿卡蒂奥

最新推荐文章于 2022-09-23 22:34:41 发布

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分类专栏： FPGA/CPLD 文章标签：学习 fpga开发

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输入输出映射关系

在这里插入图片描述

VHDL code

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity LEDcontrol is
	port(
		i_lamp_val:in std_logic_vector(3 downto 0);
		i_sys_res:in std_logic;
		o_lamp_display_val:out std_logic_vector(9 downto 0)
	);
end entity LEDcontrol;
architecture behavel of LEDcontrol is
	signal r_lamp_display_val: std_logic_vector(9 downto 0);
	begin
		process(i_sys_res, i_lamp_val)
			begin
				if(i_sys_res='1')then
					r_lamp_display_val<="0000000000";--中间变量
				else
					case i_lamp_val is
						when "0000" => r_lamp_display_val <="0000000001";
						when "0001" => r_lamp_display_val <="0000000010";
						when "0010" => r_lamp_display_val <="0000000100";
						when "0011" => r_lamp_display_val <="0000001000";
						when "0100" => r_lamp_display_val <="0000010000";
						when "0101" => r_lamp_display_val <="0000100000";
						when "0110" => r_lamp_display_val <="0001000000";
						when "0111" => r_lamp_display_val <="0010000000";
						when "1000" => r_lamp_display_val <="0100000000";
						when "1001" => r_lamp_display_val <="1000000000";
						when others => r_lamp_display_val <="0000000000";
						end case;
					end if;
				end process;
				o_lamp_display_val<=r_lamp_display_val;
end architecture behavel;