Core name: Xilinx LogiCORE Serial RapidIO
Version: 5.5
Release Date: April 19, 2010
================================================================================
This document contains the following sections:
1. Introduction
2. New Features
3. Supported Devices
4. Resolved Issues
5. Known Issues
6. Technical Support
7. Other Information (optional)
8. Core Release History
9. Legal Disclaimer
================================================================================
1. INTRODUCTION
For the most recent updates to the IP installation instructions for this
core, please go to:
http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
For system requirements:
http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
This file contains release notes for the Xilinx LogiCORE IP Serial RapidIO v5.5
solution. For the latest core updates, see the product page at:
http://www.xilinx.com/rapidio/
2. NEW FEATURES
- ISE 12.1 software support
- Designed to RapidIO Interconnect Specification v2.1
- Virtex-6 LXT/HXT/SXT 5.0 Gbps support
- Spartan-6 3.125 Gbps and 4x support
- Expanded simulator support
- Support for ML505, ML605 and SP605 boards (see Release Notes AR for details)
3. SUPPORTED DEVICES
- Virtex-6 LXT/HXT/SXT/CXT
- Spartan-6 LXT
- Virtex-5 LXT/FXT/SXT
- Virtex-4 FX
4. RESOLVED ISSUES
- PHY does not properly pass CRF bit to Buffer
- Version fixed : v5.5
- CR# 519603 - Updated PHY to properly pass CRF
- GT settings for Spartan-6 and Virtex-6 updated based on characterization
- Version fixed : v5.5
- PORT_INITIALIZED toggles indefinitely
- Version fixed : v5.5
- CR# 551271 - GT wrappers updated so that the core will detect invalid
data until RESETDONE asserts.
- Processing Element Features CAR implemented incorrectly
- Version fixed : v5.5
- CR# 528369 - Part of the PEF CAR was implemented in the PHY
configuration space, now it is merged into the LOGIO configuration
space as directed by the spec. See core User Guide for map of
configuration space.
- Recommended modifications to Example Design reset scheme
- Version fixed : v5.5
- CR# 533208, 533209, 533212 - Updated reset sequence, see AR# 33574 for
specifics.
- Example design "implement.bat" file has error
- Version fixed : v5.5
- CR# 533796 - Corrected syntax for NGDBuild command.
- Virtex-6 clock modules not using production MMCM settings
- Version fixed : v5.4rev1
- CR#546021 - Using outdated values from the clocking wizard in clock
modules.
- Buffer BRAM using READ_FIRST mode
- Version fixed : v5.4rev1
- CR#546424 - Using READ_FIRST mode for buffer BRAMs - need to update to
WRITE_FIRST mode for Spartan-6 and Virtex-6 based on characterization.
- VHDL example design simulation error when CRF bit de-selected
- Version fixed : v5.4rev1
- CR# 532020 - Updated example design so that CRF signals not added
when CRF support is disabled.
- Virtex-6 bring-up issues
- Version fixed : v5.4
- CR#527725, CR#525309, CR#531695 - Using integer values for the MMCM_ADV,
regenerated Virtex-6 wrappers based on general hardware characterization
results, revised reset sequence. Please see core Release Notes
for updates.
- GUI settings incorrect or not properly reflected in hardware.
- Version fixed : v5.4
- CR#507334, CR#528369, CR#528370 / AR#32122 - The following register
fields were corrected: Re-transmit Suppression mask, Logical Layer
extended features pointer, DeviceVendorID.
- Latches inferred in VHDL example design
- Version fixed: v5.2
- CR#509670 / AR#32189 - Added intermediate values for partial
register and combinational assignments.
- lnk_trdy_n does not assert in evaluation core simulations
- Version fixed : v5.1rev1
- CR#493479 / AR#31864 - Modified initial state in evaluation cores.
- PHY won't generate stand-alone due to missing module
- Version fixed : v5.1rev1
- CR#493162 / AR#31834 - Shared file between buffer and log added to
buffer file list.
- Virtex-4 core has long initialization time
- Version fixed : v5.1rev1
- CR#481684 / AR#31617 - Virtex-4 initSM modified to prevent branch to
silent when RX PCS resets in DISCOVERY state.
- LogIO local arbitration doesn't account for valid causing re-arbitration
prior to legitimatepacket completion.
- Version fixed : v5.1
- CR#478748 - Valid used to gate mresp_eof_n and iresp_eof_n for local
arbitration.
- A ireq_dsc_n asserted for an undefined packet type does not get propogated
by the logical layer.
- Version fixed : v5.1
- CR#478541 - undefined packet type decode now passes dsc to buffer
allowing packet to be dropped.
- 16-bit deviceID cores may see a maintenance response transaction presented
but not validated on the IResp interface resulting in a lost transaction.
by the logical layer.
- Version fixed : v5.1
- CR#474894 - Fixed issue when the maintenance response is followed
immediatly by a single DWord SWrite packet.
- SourceID not configureable for IReq port.
- Version fixed : v5.1
- CR#473938 - Added ireq_src_id port to logical layer. All transmit source
IDs should now be configureable and all received destination IDs
observable.
- Write enables into LogIO registers aren't allowing partial register writes.
- Version fixed : v5.1
- CR#473441 - Write enables now implementedfor all LogIO registers allowing
byte-wise writes of CSRs such as the deviceID register and BAR.
- Message response transaction received as a user defined packet type using
16-bit device IDs appears as a corrupted packet on the IResp interface.
- Version fixed : v5.1
- CR#473400, CR#473693 - Fixed LogIO RX to properly handle all
user-defined types.
- PHY core does not dsc upon retry when coincident with TX packet eof
resulting in potential buffer lock-up
- Version fixed : v4.4rev2
- CR#478246 / AR#31407 - lnk_tdst_dsc_n now asserted for all retry and
error scenarios.
- Retry of packet being sent causes packet to get stuck in buffer
- Version fixed : v4.4rev2
- CR#477217 / AR#31318 - No longer applicable, v5.1 introduces new buffer.
- Core accepts muddled packet when reinitializing during packet receipt
- Version fixed : v4.4rev1
- CR#477115 / AR#31308 - Core PNAs packet in receipt when link goes down.
- Core LCSBA implementation removes 64MB of possible addressing space.
- Version fixed : v4.4
- CR#472992 / AR#30939 - Use 10-bit mask with full 34-bit address for
LCSBA intercept.
- CRC error on stalled packet
- Version fixed : v4.4
- CR#469678 / AR#30940 - Fixed condition which loaded in new CRC sequence
on a stall just after sof received by PHY. This is a non-concern for
Xilinx buffer users.
- Virtex-4 4x core may intermittenly train down to 1x mode
- Version fixed : v4.4
- CR#467616 / AR#30314 - Modified oplm_pcs_rst_sequence.v file supplied
with the core to register asynchronous TXLOCK and RXLOCK signals.
- Re-initialization not forced following a change to Port Width Override
- Version fixed : v4.4
- CR#459427 / AR#30323 - Modified PHY Layer to detect a change in the
port width override field and reinitialize when updated.
- Messaging packets providing incorrect treq_byte_count value
- Version fixed : v4.4
- CR#467116 / AR#30320 - Modified Logical Layer to properly decode
Messaging size field. Modified testbench to properly check byte
count for messaging type packets.
- 8-bit SWrite transactions usign 16-bit deviceIDs suffer lost eofs
- Version fixed : v4.4
- CR#467668 / AR#30322 - Modified Logical Layer to properly forward
eof through the pipeline.
- Some Logical Layer CARs are not being set correctly in the core.
- Version fixed : v4.4
- CR#458414 / AR#30054 - The following Logical Layer CARs are not being
set correctly in the core:
- Assembly Information CAR (offset 0xC) - ExtendedFeaturesPtr portion
- Processing Element Features CAR (offset 0x10)
- Switch Port Information CAR (offset 0x14)
- Destination Operations CAR (offset 0x1C)
- Switch Route Table Destination ID Limit CAR (offset 0x34)
- Core does not have functionality to enable the user to drop unintended
packets based on Device ID.
- Version fixed: v4.3.
- CR#455552 - Added a new port called deviceid which indicates the
current Device ID value stored in the Base Device ID CSR.
- Receive side buffer design may corrupt packets - user may see corrupted
packets from the logical layer when many small packets cause the status
FIFO to fill.
- Version fixed: v4.2
- CR#447884 / AR#29263 - No longer applicable, v5.1 introduces new buffer.
- Repeated, transmitted packet accepted control symbols referencing the
same AckID cause loss of AckID sync - The user will see this as
potentially duplicated received packets which ultimately result in a port
error condition.
- Version fixed: v4.2
- CR#444561 / AR#29233 - Modified the transmit encoder to send a single
packet accepted symbol per back-to-back control symbol.
- Stomped packet sent after RFR (Restart-from-Retry)control symbol -
The user will occasionally see error recovery on a retry which will affect
system bandwidth.
- Version fixed: v4.2
- CR#435188 / AR#24837 - Modified the PHY interface to kill a packet if
discontinued on eof and prevent entry to the buffer.
5. KNOWN ISSUES
The following are known issues for v5.5 of this core at time of release:
- NGDBuild errors when using ISE GUI unless XST Keep Hierarchy set to Soft
- Version to be fixed : Fix Not Scheduled
- CR#534514 / AR#33528 - Please reference the Answer Record for additional
information and recommendations.
- Virtex-4 FX 3.125G, 4x core may not meet timing.
- Version to be fixed : Fix Not Scheduled
- CR#506364 / AR#32195 - Please reference the Answer Record for additional
information and recommendations.
- Unable to traindown to x1 mode in Lane 2.
- Version to be fixed : Fix Not Scheduled
- CR#457109 / AR#30023 - Traindown in Lane 0 works successfully but the
Serial RapidIO endpoint is unable to traindown to Lane 2. The RocketIO
transceivers only allow traindown to the channel bonding master.
- Core reinitialization during error recovery causes recoverable protocol
error.
- Version to be fixed : Fix Not Scheduled
- CR#457885 / AR#30021 - This is an corner condition that could occur if
core is forced to reinitialize (i.e. - force_reinit) while it is in the
process of error recovery. If this condition occurs, packets will be
sent during recovery's quiet period. This situation is recoverable.
- Post-Synplicity synthesis implementation runs may exhibit ucf failures
- Version to be fixed : Fix Not Scheduled
- CR#447782 / AR#29522 - Synplicity generated net names are not
consistent with XST generated names and may not be consistent between
core types. The .ucf file must be edited in these failure cases. Please
reference the Serial RapidIO v5.1 web Release Notes for suggested work
around.
- PNA cause field may occasionally reflect a reserved value
- Version to be fixed : Fix Not Scheduled
- CR#436767 / AR#24982 - The cause field is for debug purposes only
and will not affect functionality. Occurrence is rare and requires
alignment of multiple control symbols.
- Control Symbols may be lost on reinit
- Version to be fixed : Fix Not Scheduled
- CR#436768 / AR#24970 - This is an unusual and ultimately recoverable
error. Set the "Additional Link Request Before Fatal" value on the
Physical Configuration page of the GUI to "4" in order to prevent a
lost Link Request or Link Response from causing the core to enter
the port error state.
- Logical Rx does not support core side stalls
- Version to be fixed : Fix Not Scheduled
- CR#436770 / AR#24968 - The rx buffer must provide packets to the
logical layer without buffer induced stall cycles. The buffer
reference design provided with the core is a store and forward
buffer and complies with this rule.
The most recent information, including known issues, workarounds, and
resolutions for this version is provided in the IP Release Notes Guide
located at
www.xilinx.com/support/documentation/user_guides/xtp025.pdf
6. TECHNICAL SUPPORT
To obtain technical support, create a WebCase at www.xilinx.com/support.
Questions are routed to a team with expertise using this product.
Xilinx provides technical support for use of this product when used
according to the guidelines described in the core documentation, and
cannot guarantee timing, functionality, or support of this product for
designs that do not follow specified guidelines.
7. OTHER INFORMATION
- N/A
8. CORE RELEASE HISTORY
Date By Version Description
================================================================================
04/2010 Xilinx, Inc. 5.5 5.0 Gbps support
03/2010 Xilinx, Inc. 5.4 Revision 1 11.5 support/Patch Release
09/2009 Xilinx, Inc. 5.4 Spartan-6 support
06/2009 Xilinx, Inc. 5.3 Virtex-6 support
04/2009 Xilinx, Inc. 5.2 11.1i support
11/2008 Xilinx, Inc. 5.1 Revision 1 Patch Release
09/2008 Xilinx, Inc. 5.1 New Buffer LogiCore
07/2008 Xilinx, Inc. 4.4 Revision 2 Patch Release
07/2008 Xilinx, Inc. 4.4 Revision 1 Patch Release
06/2008 Xilinx, Inc. 4.4 Bug Fixes
03/2008 Xilinx, Inc. 4.3 10.1i support
10/2007 Xilinx, Inc. 4.2 9.2i support
02/2007 Xilinx, Inc. 4.1 9.1i support
02/2006 Xilinx, Inc. 3.1 Revision 1 Patch Release
01/2006 Xilinx, Inc. 3.1 8.1i support
================================================================================
9. Legal Disclaimer
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