When both FV and LV are asserted, the pixel is valid. PIXCLK cycles that occur when FV isde-asserted are called vertical blanking. PIXCLK cycles that occur when only LV isde-asserted are called horizontal blanking.
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asserted: 把信号变为active,根据系统要求不同,该有效电平可以是高电平(即高有效),也可以是低电平(即低有效)。
de-asserted : 同上,只是刚好相反,为失效信号。