使用Coreinfo工具查看电脑CPU相关信息（cache，NUMA node，socket ）

官网下载链接

 Download Coreinfo

使用教程：

Coreinfo - Windows Sysinternals | Microsoft Docs

 简介

CoreInfo是一个命令行实用程序，它向您介绍逻辑处理器和物理处理器，NUMA节点和它们所在的套接字之间的映射，以及分配给每个逻辑处理器的缓存。

它使用Windows中GetLogicalProcessorInformation函数来获取此信息并将其打印到屏幕，表示与具有星号的逻辑处理器的映射。  '*'.CoreInfo可用于获得系统的处理器和缓存拓扑的洞察力。

安装

将zip文件提取到目录，然后通过在32位Windows版本或CoreInfo64上键入64位版本的控制台中的该目录CoreInfo来运行CoreInfo。 

使用CoreInfo

它将显示与指定资源相对应的OS可见处理器的映射，“*”表示适用的处理器。例如，在4核系统中，缓存输出中的一行，它具有由3核和4核共享的内存映射。

参数说明：coreinfo.exe [-c][-f][-g][-l][-n][-s][-m][-v]

Parameter	Description
-c	Dump information on cores.
-f	Dump core feature information.
-g	Dump information on groups.
-l	Dump information on caches.
-n	Dump information on NUMA nodes.
-s	Dump information on sockets.
-m	Dump NUMA access cost.
-v	Dump only virtualization-related features including support for second level address translation.

 具体使用方法：

将下载好的Coreinfo64.exe文件直接拖入cmd命令行中，输入相应指令，按下回车即可：

比如使用 -l 指令查看处理器的缓存类型：

C:\Users\LUO\Desktop\Coreinfo>C:\Users\LUO\Desktop\Coreinfo\Coreinfo64.exe -l

输出的信息：

Coreinfo v3.52 - Dump information on system CPU and memory topology
Copyright (C) 2008-2021 Mark Russinovich
Sysinternals - www.sysinternals.com

Logical Processor to Cache Map:
**--  Data Cache          0, Level 1,   32 KB, Assoc   8, LineSize  64
**--  Instruction Cache   0, Level 1,   32 KB, Assoc   8, LineSize  64
**--  Unified Cache       0, Level 2,  256 KB, Assoc   8, LineSize  64
****  Unified Cache       1, Level 3,    3 MB, Assoc  12, LineSize  64
--**  Data Cache          1, Level 1,   32 KB, Assoc   8, LineSize  64
--**  Instruction Cache   1, Level 1,   32 KB, Assoc   8, LineSize  64
--**  Unified Cache       2, Level 2,  256 KB, Assoc   8, LineSize  64

 从以上信息可知：

我的电脑处理器有三级缓存，缓存的cache line 的大小为64字节，一级缓存大小为32KB，分为数据缓存和指令缓存；二级缓存为Unified缓存，大小为256KB；三级缓存也为Unified缓存，大小为3MB。

从CPU到    大约需要的CPU时钟周期                            大约需要的时间
主存                                                                                约60-80ns
QPI            总线传输(between sockets, not drawn)        约20ns
L3 cache    约40-45 cycles                                             约15ns
L2 cache    约10 cycles                                                  约3ns
L1 cache    约3-4 cycles                                                约1ns
寄存器        1 cycle

GetLogicalProcessorInformation函数

#include <windows.h>
#include <malloc.h>    
#include <stdio.h>
#include <tchar.h>

typedef BOOL(WINAPI *LPFN_GLPI)(
	PSYSTEM_LOGICAL_PROCESSOR_INFORMATION,
	PDWORD);


// Helper function to count set bits in the processor mask.
DWORD CountSetBits(ULONG_PTR bitMask)
{
	DWORD LSHIFT = sizeof(ULONG_PTR) * 8 - 1;
	DWORD bitSetCount = 0;
	ULONG_PTR bitTest = (ULONG_PTR)1 << LSHIFT;
	DWORD i;

	for (i = 0; i <= LSHIFT; ++i)
	{
		bitSetCount += ((bitMask & bitTest) ? 1 : 0);
		bitTest /= 2;
	}

	return bitSetCount;
}

int _cdecl _tmain()
{
	LPFN_GLPI glpi;
	BOOL done = FALSE;
	PSYSTEM_LOGICAL_PROCESSOR_INFORMATION buffer = NULL;
	PSYSTEM_LOGICAL_PROCESSOR_INFORMATION ptr = NULL;
	DWORD returnLength = 0;
	DWORD logicalProcessorCount = 0;
	DWORD numaNodeCount = 0;
	DWORD processorCoreCount = 0;
	DWORD processorL1CacheCount = 0;
	DWORD processorL2CacheCount = 0;
	DWORD processorL3CacheCount = 0;
	DWORD processorPackageCount = 0;
	DWORD byteOffset = 0;
	PCACHE_DESCRIPTOR Cache;

	glpi = (LPFN_GLPI)GetProcAddress(
		GetModuleHandle(TEXT("kernel32")),
		"GetLogicalProcessorInformation");
	if (NULL == glpi)
	{
		_tprintf(TEXT("\nGetLogicalProcessorInformation is not supported.\n"));
		return (1);
	}

	while (!done)
	{
		DWORD rc = glpi(buffer, &returnLength);

		if (FALSE == rc)
		{
			if (GetLastError() == ERROR_INSUFFICIENT_BUFFER)
			{
				if (buffer)
					free(buffer);

				buffer = (PSYSTEM_LOGICAL_PROCESSOR_INFORMATION)malloc(
					returnLength);

				if (NULL == buffer)
				{
					_tprintf(TEXT("\nError: Allocation failure\n"));
					return (2);
				}
			}
			else
			{
				_tprintf(TEXT("\nError %d\n"), GetLastError());
				return (3);
			}
		}
		else
		{
			done = TRUE;
		}
	}

	ptr = buffer;

	while (byteOffset + sizeof(SYSTEM_LOGICAL_PROCESSOR_INFORMATION) <= returnLength)
	{
		switch (ptr->Relationship)
		{
		case RelationNumaNode:
			// Non-NUMA systems report a single record of this type.
			numaNodeCount++;
			break;

		case RelationProcessorCore:
			processorCoreCount++;

			// A hyperthreaded core supplies more than one logical processor.
			logicalProcessorCount += CountSetBits(ptr->ProcessorMask);
			break;

		case RelationCache:
			// Cache data is in ptr->Cache, one CACHE_DESCRIPTOR structure for each cache. 
			Cache = &ptr->Cache;
			if (Cache->Level == 1)
			{
				processorL1CacheCount++;
			}
			else if (Cache->Level == 2)
			{
				processorL2CacheCount++;
			}
			else if (Cache->Level == 3)
			{
				processorL3CacheCount++;
			}
			break;

		case RelationProcessorPackage:
			// Logical processors share a physical package.
			processorPackageCount++;
			break;

		default:
			_tprintf(TEXT("\nError: Unsupported LOGICAL_PROCESSOR_RELATIONSHIP value.\n"));
			break;
		}
		byteOffset += sizeof(SYSTEM_LOGICAL_PROCESSOR_INFORMATION);
		ptr++;
	}

	_tprintf(TEXT("\nGetLogicalProcessorInformation results:\n"));
	_tprintf(TEXT("Number of NUMA nodes: %d\n"),
		numaNodeCount);
	_tprintf(TEXT("Number of physical processor packages: %d\n"),
		processorPackageCount);
	_tprintf(TEXT("Number of processor cores: %d\n"),
		processorCoreCount);
	_tprintf(TEXT("Number of logical processors: %d\n"),
		logicalProcessorCount);
	_tprintf(TEXT("Number of processor L1/L2/L3 caches: %d/%d/%d\n"),
		processorL1CacheCount,
		processorL2CacheCount,
		processorL3CacheCount);

	free(buffer);

	return 0;
}

打印出的结果：

GetLogicalProcessorInformation results:
Number of NUMA nodes: 1
Number of physical processor packages: 1
Number of processor cores: 2
Number of logical processors: 4
Number of processor L1/L2/L3 caches: 4/2/1