FPGA-verilog语言练习-HDLBits

HDL练习题总结（一）

1. HDLBit网站介绍

   关于Verilog HDL语言的学习我刚刚开始，通过查看一些博客和学习体会注意到了HDLBits这个网站，有一些关于该语言编程的练习题对初学者理解和联系十分友好。通过模拟仿真并对比远程数据库来检查错误。
   网站链接：https://hdlbits.01xz.net/wiki/Main_Page
   网站首页效果图：
   
   做题练习展示：
   
   
   由于网站更新了许多的内容，在网上找到了wangbowj123博友编辑的部分题目的参考答案。这里附上博文链接：https://blog.csdn.net/wangbowj123/article/details/105677327

更新：最近刚刚找到了HDLBits比较全面的参考答案，wangkai_2019博主在20年就更新了较为全面的答案参考，同时品论的一些答案修正也是十分不错的，再次对博友表示尊敬，一下附文章链接：
https://blog.csdn.net/wangkai_2019/article/details/106664283
本文仅此作为一个自我学习笔记，若其中答案有所错误或更好的参考，欢迎指正，十分感谢。

后续代码展示：

2. verilog language

2.5 More Verilog Features

01.Conditional
Conditional ternary operator

module top_module (
    input [7:0] a, b, c, d,
    output [7:0] min);//

    wire [7:0] q1,q2;
    assign q1 = (a<b)? a:b;
    assign q2 = (q1<c)? q1:c;
    assign min = (q2<d)? q2:d;
endmodule

02.reduction
Reduction operators

module top_module (
    input [7:0] in,
    output parity); 
    assign parity = ^in;
endmodule

03.Gates100
Reduction: Even wider gates

module top_module( 
    input [99:0] in,
    output out_and,
    output out_or,
    output out_xor 
);
    assign out_and = ∈
    assign out_or = |in;
    assign out_xor = ^in;
    
endmodule

04.Vector100r
Combinational for-loop: Vector reversal 2

//方法一：暴力代码
module top_module( 
    input [99:0] in,
    output [99:0] out
);
    assign out = {in[0],in[1],in[2],in[3],in[4],in[5],in[6],in[7],in[8],in[9],
                  in[10],in[11],in[12],in[13],in[14],in[15],in[16],in[17],in[18],in[19],
                  in[20],in[21],in[22],in[23],in[24],in[25],in[26],in[27],in[28],in[29],
                  in[30],in[31],in[32],in[33],in[34],in[35],in[36],in[37],in[38],in[39],
                  in[40],in[41],in[42],in[43],in[44],in[45],in[46],in[47],in[48],in[49],
                  in[50],in[51],in[52],in[53],in[54],in[55],in[56],in[57],in[58],in[59],
                  in[60],in[61],in[62],in[63],in[64],in[65],in[66],in[67],in[68],in[69],
                  in[70],in[71],in[72],in[73],in[74],in[75],in[76],in[77],in[78],in[79],
                  in[80],in[81],in[82],in[83],in[84],in[85],in[86],in[87],in[88],in[89],
                  in[90],in[91],in[92],in[93],in[94],in[95],in[96],in[97],in[98],in[99]};
endmodule
//方法二：generate循环
module top_module( 
    input [99:0] in,
    output [99:0] out
);
    generate
        genvar i;
        for(i = 0; i <= 99; i = i + 1)begin:reverse//注意保留名称
            assign out[i] = in[99 - i];
        end
    endgenerate
endmodule

05.popcount255
Combinational for-loop: 255-bit population count

module top_module( 
    input [254:0] in,
    output [7:0] out );

    integer i;
    always@(*)begin
        out = 0;
        for(i=0;i< 255;i=i+1)begin
                if(in[i])
                    out = out + 1; 
                else
                    out = out;
        end  
    end
endmodule

06.Adder100i
Generate for-loop: 100-bit binary adder 2

module top_module( 
    input [399:0] a, b,
    input cin,
    output cout,
    output [399:0] sum );

    wire[99:0]    cout_r;
    generate
        genvar i;
        for(i = 0; i <= 99; i = i + 1)begin:adder
            if(i == 0)begin
                bcd_fadd u_bcd_fadd(
                    .a        (a[3:0]),
                    .b        (b[3:0]),
                    .cin      (cin),
                    .sum      (sum[3:0]),
                    .cout     (cout_r[0])
                );
            end
            else begin
                bcd_fadd ui_bcd_fadd(
                    .a        (a[4 * i + 3: 4 * i]),
                    .b        (b[4 * i + 3: 4 * i]),
                    .cin      (cout_r[i - 1] ),
                    .sum      (sum[4 * i + 3: 4 * i]),
                    .cout     (cout_r[i])
                );
            end
        end
        assign cout = cout_r[99];
    endgenerate
endmodule

.07.Bcdadd100
Generate for-loop: 100-digit BCD adder

module top_module( 
    input [399:0] a, b,
    input cin,
    output cout,
    output [399:0] sum );
    
    genvar i;
    reg	[100:0] r_cin;
    always@(*) r_cin[0]=cin;
    generate
        for(i=1;i<=100;i=i+1)
        begin:gen
            bcd_fadd bcd_fadd_inst(
                .a(a[(i*4-1)-:4]),
                .b(b[(i*4-1)-:4]),
                .cin(r_cin[i-1]),
                .cout(r_cin[i]),
            .sum(sum[(i*4-1)-:4])
            );
        end
    endgenerate
      assign cout=r_cin[100];
endmodule

3.Circuits

3.1 Conbinational Logic

1.Basic gates
01.Exams/m2014 q4h
wire

module top_module (
    input wire in,
    output wire out);
     
    assign out = in;

endmodule

02.Exams/m2014 q4i
GND

module top_module (
    output out);
    assign out = 1'b0;
endmodule

03.Exams/m2014 q4e
nor

module top_module (
    input in1,
    input in2,
    output out);
    assign out = ~(in1|in2);//按位取反
    //assign out = !(in1|in2);//逻辑取反
endmodule

04.Exams/m2014 q4f
another gates

module top_module (
    input in1,
    input in2,
    output out);
    
    assign out = in1 & (~in2);

endmodule

05.Exams/m2014 q4g
two gates

module top_module (
    input in1,
    input in2,
    input in3,
    output out);
    
    reg r1_out;
    assign r1_out = ~(in1^in2);
    assign out = r1_out ^ in3;

endmodule

06.gates
more logic gates

module top_module( 
    input a, b,
    output out_and,
    output out_or,
    output out_xor,
    output out_nand,
    output out_nor,
    output out_xnor,
    output out_anotb
);
    assign out_and = a&b;
    assign out_or = a|b;
    assign out_xor = a^b;
    assign out_nand = ~(a&b);
    assign out_nor = ~(a|b);
    assign out_xnor = ~(a^b);
    assign out_anotb = a&(~b);
endmodule

07.7420
7420 chip

module top_module ( 
    input p1a, p1b, p1c, p1d,
    output p1y,
    input p2a, p2b, p2c, p2d,
    output p2y );
    
    assign p1y = ~(p1a&p1b&p1c&p1d);
    assign p2y = ~(p2a&p2b&p2c&p2d);
endmodule

08.Truthtable1
truth tables

module top_module( 
    input x3,
    input x2,
    input x1,  // three inputs
    output f   // one output
);
    assign f= (x1&x3) | (x2&(~x3));

endmodule

09.Mt2015 eq2
Two-bit equality

module top_module ( input [1:0] A, input [1:0] B, output z ); 
    assign z = (A==B)?1'b1 : 1'b0;
endmodule

10.Mt2015 q4a
Simple circuit A

module top_module (input x, input y, output z);
    assign z = (x^y)&x;
endmodule

11.Mt2015 q4b
Simple circuit B

module top_module ( input x, input y, output z );
    assign z = ~(x^y);
endmodule

12.Mt2015 q4
Combine circuits A and B

module top_module (input x, input y, output z);

    wire rz1,rz2;
    assign rz1 = (x ^ y) & x;
    assign rz2 = x ~^ y;
    assign z = (rz1 |rz2) ^ (rz1&rz2);
endmodule

13.Ringer
Ring or vibrate?

module top_module (
    input ring,
    input vibrate_mode,
    output ringer,       // Make sound
    output motor         // Vibrate
);
    assign ringer = ~vibrate_mode & ring;
    assign motor = vibrate_mode & ring;
endmodule

14.Thermostat
Thermostat

module top_module (
    input too_cold,
    input too_hot,
    input mode,
    input fan_on,
    output heater,
    output aircon,
    output fan
); 

    assign heater = mode & too_cold;
    assign aircon = (~mode) & too_hot;
    assign fan = (heater | aircon )|fan_on;
endmodule

15.Popcount3
3-bit population count

module top_module( 
    input [2:0] in,
    output [1:0] out );
    reg [1:0] r_out;
    always@(*)
        case(in)
            3'b000:r_out = 2'b00;
            3'b001:r_out = 2'b01;
            3'b010:r_out = 2'b01;
            3'b011:r_out = 2'b10;
            3'b100:r_out = 2'b01;
            3'b101:r_out = 2'b10;
            3'b110:r_out = 2'b10;
            3'b111:r_out = 2'b11;
        endcase
    assign out = r_out;  
endmodule

16.Gatesv
Gates and vectors

module top_module( 
    input [3:0] in,
    output [2:0] out_both,
    output [3:1] out_any,
    output [3:0] out_different );
    assign out_both[0] = in[0]&in[1];
    assign out_both[1] = in[2]&in[1];
    assign out_both[2] = in[2]&in[3];
    
    assign out_any[3] = in[3]|in[2];
    assign out_any[2] = in[2]|in[1];
    assign out_any[1] = in[1]|in[0];
    
    assign out_different[0] = (in[0]&(~in[1])) | ((~in[0])&in[1]);
    assign out_different[1] = (in[1]&(~in[2])) | ((~in[1])&in[2]);
    assign out_different[2] = (in[2]&(~in[3])) | ((~in[2])&in[3]);
    assign out_different[3] = (in[3]&(~in[0])) | ((~in[3])&in[0]);
 //快捷方法，更简洁节省资源。
//assign out_both = in[3:1] & in[2:0];
//assign out_any = in[3:1] | in[2:0];
//assign out_different = {in[0], in[3:1]} ^ in;

    
endmodule

17.Gatesv100
Even longer vectors

module top_module( 
    input [99:0] in,
    output [98:0] out_both,
    output [99:1] out_any,
    output [99:0] out_different );

    assign out_both = in[99:1] & in[98:0];
    assign out_any = in[99:1] | in[98:0];
    assign out_different = {in[0], in[99:1]} ^ in;
endmodule

3.1.2 Multipuexers

1.Mux2to1
2-to-1 multiplexer

    module top_module( 
        input a, b, sel,
        output out ); 
        assign out = sel? b:a;
    endmodule

2.Mux2to1v
2-to-1 bus multiplexer

module top_module( 
    input [99:0] a, b,
    input sel,
    output [99:0] out );

    assign out = sel? b:a;
endmodule

3.Mux9to1v
9-to-1 multiplexer

module top_module( 
    input [15:0] a, b, c, d, e, f, g, h, i,
    input [3:0] sel,
    output [15:0] out );
    always@(*)
        case(sel)
            4'd0:out = a;
            4'd1:out = b;
            4'd2:out = c;
            4'd3:out = d;
            4'd4:out = e;
            4'd5:out = f;
            4'd6:out = g;
            4'd7:out = h;
			4'd8:out = i;
            4'd9,4'd10,4'd11,4'd12,4'd13,4'd14,4'd15: out = 16'hffff;
        endcase 
endmodule

4.Mux256to1
256-to-1 multiplexer

module top_module( 
    input [255:0] in,
    input [7:0] sel,
    output out );
    assign out =in[sel];
endmodule

5.Mux256to1v
256-to-1 4-bit multiplexer

module top_module( 
    input [1023:0] in,
    input [7:0] sel,
    output [3:0] out );
   
   assign out = in[sel*4 + :4];    
    
    //assign out[0] = in[sel*4];
   // assign out[1] = in[sel*4 + 1];
    //assign out[2] = in[sel*4 + 2];
   // assign out[3] = in[sel*4 + 3];
   
endmodule

3.1.3 Arithmetic Circuits

1.Hadd
Half adder

module top_module( 
    input a, b,
    output cout, sum );
    
    assign sum = a ^ b;
    assign cout = a&b;
endmodule

2.Fadd
Full adder

module top_module( 
    input a, b, cin,
    output cout, sum );

    assign sum = (~a)&(b^cin) | a&(b~^cin);
    assign cout = a&b | cin&(a^b);
endmodule

3.Adder3
3-bit binary adder

module top_module( 
    input [2:0] a, b,
    input cin,
    output [2:0] cout,
    output [2:0] sum );
    full_adder f_adder_1 ( .a(a[0]), .b(b[0]), .cin(cin), .cout(cout[0]), .sum(sum[0]) ); 
    full_adder f_adder_2 ( .a(a[1]), .b(b[1]), .cin(cout[0]), .cout(cout[1]), .sum(sum[1]) ); 
    full_adder f_adder_3 ( .a(a[2]), .b(b[2]), .cin(cout[1]), .cout(cout[2]), .sum(sum[2]) ); 
endmodule 
module full_adder( input a, input b, input cin, output cout, output sum); 
    assign sum = a ^ b ^ cin; 
    assign cout= a & cin | b & cin | a & b;

endmodule

4.Exams/m2014 q4j
Adder
···