weixin_42799603的博客

利用new关键字生成动态二维数组并传递给函数#include<iostream>using namespace std;int sum_apple(int **arr, int Size, int n);int sum_apple1(const int(*arr)[4], int Size);void show(int **arr, int Size, int n);int main(){ const int apple[3][4] = { {1, 2, 3, 4},

组合逻辑竞争冒险，时序逻辑亚稳态【0型冒险和1型冒险及其消除方法】

FPGA时序分析之关键路径（Critical Path）【华为静态时序分析资料】【笔试面试】

DFT（Design for Test）可测性设计【FPGA探索者】

FPGA中亚稳态

理论参考：异步FIFO—Verilog实现异步FIFO——结构、Verilog代码实现与仿真引用红色闪电007的评论：异步FIFO使用格雷码的唯一目的就是"即使在亚稳态进行读写指针抽样也能进行正确的空满状态判断"。 在异步的FIFO中，采用格雷码进行计数，相邻的数据仅仅只有1bit变化，这样在两个时钟域同步的时候仅仅可能只有1bit产生亚稳态，通过同步以后，亚稳态可以消除，最坏的情况是这1bit采错，但是即使是采错地址也只是相差1个，这对判断空满标志不会产生影响。 如果是采用10十进制进行编码，则相

理论：参考《正点原子逻辑设计指南》module s_fifo( input clk, input rst, input wr_en, input rd_en, input [7:0] data_in, output reg [7:0] data_out, output reg empty,

参考文章【设计经验】5、Verilog对数据进行四舍五入（round）与饱和（saturation）截位当前还有存疑，请大家指正题目：请用Verilog实现算法 Q = K * (D - 16)，其中输入数据D和输出数据D和输出数据Q都是无符号8位整数（无符号，8位整数，0位小数），输入参数K的数值为13Q10（共13位，1位符号位，10位小数位），中间过程保留完整精度，最后四舍五入。答案11.先按照参考文章得到有符号整数输出，然后变到无符号输出assign Q = Q1 + 128;转成无符

参考文章杰之行-CDC：跨时钟域处理李锐博恩-谈谈跨时钟域传输问题（CDC）目前理解水平，记录一下，有问题还请指教文章目录1 单比特信号的跨时钟域处理1.1 慢时钟域到快时钟域1.1.1 两级触发器同步1.1.2 边沿检测同步器1.1.2.1 信号上升沿检测1.1.2.2 信号下降沿检测1.1.2.3 信号双沿检测1.1.3 握手处理1.2 快时钟域到慢时钟域1.2.1 电平拓展1.2.2 脉冲同步器1.2.3 握手处理2 多比特信号的跨时钟域处理2.1 两级触发器2.2 格需码编码2.3 异步FI

Mealy型module sqe_de_MTK_2018( input clk, input rst_n, input in, output out ); parameter st0 = 2'b00; parameter st1 = 2'b01; parameter st2 = 2'b10; reg [1:0] state = st0,next_state; reg out.

题目没有说序列重叠检测与否，只考虑重叠检测module seq_de( input clk, input reset, input x, output z1, output z2 ); parameter s0 = 3'd0, s1 = 3'd1, s2 = 3'd2, s3 = 3'd3, s4 = 3'd4, s5 = 3'd5, s6 = 3'd6; reg [2:0] state = 3'd0,next_state; .

6-146-15z1z2目前总结的规律1. s0状态与检测序列的第一位相反2. 检测序列重叠还是不重叠不同在于最后一个状态的变化

题目Implement a Mealy-type finite state machine that recognizes the sequence “101” on an input signal named x. Your FSM should have an output signal, z, that is asserted to logic-1 when the “101” sequence is detected. Your FSM should also have an active-low

题目Synchronous HDLC framing involves decoding a continuous bit stream of data to look for bit patterns that indicate the beginning and end of frames (packets). Seeing exactly 6 consecutive 1s (i.e., 01111110) is a “flag” that indicate frame boundaries. To

atom运行.py文件安装python 参考scdn菜逼的文章，注意添加环境变量安装atom，下载atom-runner，参考[Anniesama的文章]，(https://blog.csdn.net/qq_20169819/article/details/79144455)创建一个.py格式的文件，输入简单的python代码，Alt+r运行代码若需要numpy等库，安装参考NumPy 安装 | 菜鸟教程中结合cmd使用 pip 安装之镜像安装pip安装我之前安装好了，只是记录一下运行结

题目：module top_module( input clk, input areset, // Freshly brainwashed Lemmings walk left. input bump_left, input bump_right, input ground, output walk_left, output walk_right, output aaah ); parameter LEFT = 0, RI

题目：The game Lemmings involves critters with fairly simple brains. So simple that we are going to model it using a finite state machine.In the Lemmings’ 2D world, Lemmings can be in one of two states: walking left or walking right. It will switch directio

题目：The following is the state transition table for a Moore state machine with one input, one output, and four states. Use the following one-hot state encoding: A=4’b0001, B=4’b0010, C=4’b0100, D=4’b1000.Derive state transition and output logic equations

题目：This is a Moore state machine with two states, one input, and one output. Implement this state machine. Notice that the reset state is B.This exercise is the same as fsm1s, but using asynchronous reset.module top_module( input clk, input are

题目：Build a 4-digit BCD (binary-coded decimal) counter. Each decimal digit is encoded using 4 bits: q[3:0] is the ones digit, q[7:4] is the tens digit, etc. For digits [3:1], also output an enable signal indicating when each of the upper three digits shoul