1、Andgate
module top_module(
input a,
input b,
output out );
assign out = a&b;
endmodule
2、Norgata
module top_module(
input a,
input b,
output out );
assign out = ~(a|b);
endmodule
3、Xnorgate(同或)
module top_module(
input a,
input b,
output out );
assign out = ~a^b;
endmodule
4、wire_decl
`default_nettype none
module top_module(
input a,
input b,
input c,
input d,
output out,
output out_n );
wire and1;
wire and2;
wire or1;
assign and1 = a&b;
assign and2 = c&d;
assign or1 = and1|and2;
assign out = or1;
assign out_n = ~or1;
endmodule
5、7458
module top_module (
input p1a, p1b, p1c, p1d, p1e, p1f,
output p1y,
input p2a, p2b, p2c, p2d,
output p2y );
assign p2y = (p2a&p2b)|(p2c&p2d);
assign p1y = (p1a&p1b&p1c)|(p1d&p1e&p1f);
endmodule
6、vector0
module top_module (
input wire [2:0] vec,
output wire [2:0] outv,
output wire o2,
output wire o1,
output wire o0 ); // Module body starts after module declaration
assign outv = vec;
assign o0 = vec[0],o1 = vec[1],o2 = vec[2];
endmodule
7、Vector1
`default_nettype none // Disable implicit nets. Reduces some types of bugs.
module top_module(
input wire [15:0] in,
output wire [7:0] out_hi,
output wire [7:0] out_lo );
assign out_hi = in[15:8];
assign out_lo = in[7:0];
endmodule
8、Vector2
module top_module(
input [31:0] in,
output [31:0] out );//
assign out[31:24] = in[7:0];
assign out[23:16] = in[15:8];
assign out[15:8] = in[23:16];
assign out[7:0] = in[31:24];
endmodule
9、Vector3
module top_module(
input [2:0] a,
input [2:0] b,
output [2:0] out_or_bitwise,
output out_or_logical,
output [5:0] out_not
);
assign out_or_bitwise = a|b;
assign out_or_logical = a||b;
assign out_not = {~b,~a};
endmodule
10、Gates4
module top_module(
input [3:0] in,
output out_and,
output out_or,
output out_xor
);
assign out_and = ∈
assign out_or = |in;
assign out_xor = ^in;
endmodule
11、A Bit of Practice
`
module top_module (
input [4:0] a, b, c, d, e, f,
output [7:0] w, x, y, z );//
assign w = { a,b[4:2]};
assign x = { b[1:0],c,d[4]};
assign y = { d[3:0],e[4:1]};
assign z = { e[0],f,2'b11};
//or assign {w,x,y,z} = { a,b,c,d,e,f,2'b11};
endmodule
12、Vectorr
module top_module(
input [7:0] in,
output [7:0] out
);
integer i;
always@(*)begin
for(i=0;i<8;i=i+1)begin
out[i] = in[7-i];
end
end
endmodule
//或者
generate
genvar i;
for(i=0;i<8;i=i+1)begin:my_block_name
assign out[i] = in[7-i]; //综合过程中生成了8个assign语句
end
endgenerate
for 循环描述了电路的行为,而不是电路的结构,因此,for 循环必须置于比如 always 块这样的过程块中。(描述电路行为)for 循环表示的代码将被综合器解析,for 循环将被分别解析为硬件电路。(不过在仿真中,确实按照循环处理)。
generate 生成块很有意思的一点是,虽然在 generate ,endgenerate 之间使用的仍然是 for 循环,但生成块的概念和上面的 for 循环完全不同。
for 循环和 Verilog 中其他的几种循环语句 while ,forever,repeat 本质上都用于控制语句的执行次数。但生成块主要用于动态生成语句,例化 something(不只是例化模块),生成块与上述的过程块循环语句不同,并不是描述电路的一种行为。
生成块可以例化 assign 语句,模块,信号和变量的声明以及 always initial 这样的过程块。循环生成块是生成块中的一种类型,在综合过程中同样被综合器进行编译,这个过程可以看做综合过程中动态生成更多 Verilog 代码的预处理过程。在上面的例子中,generate 块在综合的过程中,综合了 8 句 assign 赋值语句。
总的来说,for 循环强调了对电路的行为描述,在综合的过程中循环展开,而生成块则用于综合过程中,动态生成代码,两者有本质上的不同。
13、A Bit of Practice
module top_module (
input [7:0] in,
output [31:0] out );//
assign out = { {25{in[7]}} , in[6:0] };
endmodule
14、Vector5
module top_module (
input a, b, c, d, e,
output [24:0] out );//
assign out = ~{{5{a}},{5{b}},{5{c}},{5{d}},{5{e}}}^{{5{a,b,c,d,e}}};
endmodule
15、Module
module top_module ( input a, input b, output out );
mod_a mod_a(.in1(a),.in2(b),.out(out));
endmodule
16、Module pos
module top_module (
input a,
input b,
input c,
input d,
output out1,
output out2
);
mod_a mod_a1(
out1,out2,a,b,c,d//未知端口名称,按顺序连接
);
endmodule
17、Module name
module top_module (
input a,
input b,
input c,
input d,
output out1,
output out2
);
mod_a mod_a(.out1(out1),.out2(out2),.in1(a),.in2(b),.in3(c),.in4(d));
endmodule
18、Module shift
module top_module ( input clk, input d, output q );
wire q0,q1;
my_dff my_dff0(clk,d,q0);
my_dff my_dff1(clk,q0,q1);
my_dff my_dff2(clk,q1,q);
endmodule
19、Module shift8
module top_module (
input clk,
input [7:0] d,
input [1:0] sel,
output [7:0] q
);
wire [7:0]q0;
wire [7:0]q1;
wire [7:0]q2;
my_dff8 name0(clk,d,q0);
my_dff8 name1(clk,q0,q1);
my_dff8 name2(clk,q1,q2);
always@(*)begin
case(sel)
0:q = d;
1:q = q0;
2:q = q1;
3:q = q2;
default: ;
endcase
end
endmodule
20、Module add
module top_module(
input [31:0] a,
input [31:0] b,
output [31:0] sum
);
wire cout1;
add16 add16_1( a[15:0], b[15:0], 'd0, sum[15:0], cout1 );
add16 add16_2( a[31:16], b[31:16], cout1, sum[31:16] );
endmodule
21、16个1位全加器
module top_module (
input [31:0] a,
input [31:0] b,
output [31:0] sum
);//
wire cout1;
add16 add16_1(a[15:0],b[15:0],1'b0,sum[15:0],cout1);
add16 add16_2(a[31:16],b[31:16],cout1,sum[31:16]);
endmodule
module add1 ( input a, input b, input cin, output sum, output cout );
assign sum = a^b^cin;
assign cout = a&b | a&cin | b&cin;
endmodule
22、Module cseladd 行波进位加法器
module top_module(
input [31:0] a,
input [31:0] b,
output [31:0] sum
);
wire cout1;
wire [15:0]sum1,sum2;
add16 add16_1(a[15:0],b[15:0],1'b0,sum[15:0],cout1);
add16 add16_2(a[31:16],b[31:16],1'b0,sum1);
add16 add16_3(a[31:16],b[31:16],1'b1,sum2);
assign sum[31:16] =cout1? sum2:sum1;
endmodule
23、加减法器
module top_module(
input [31:0] a,
input [31:0] b,
input sub,
output [31:0] sum
);
wire cout1;
wire [31:0]b_inv;
assign b_inv = b^{32{sub}};//sub 可编辑的非门
add16 add16_1(a[15:0],b_inv[15:0],sub,sum[15:0],cout1);
add16 add16_2(a[31:16],b_inv[31:16],cout1,sum[31:16]);
endmodule
24、always语句
module top_module(
input a,
input b,
output wire out_assign,
output reg out_alwaysblock
);
assign out_assign = a&b;
always@(*)begin
out_alwaysblock = a&b;
end
endmodule
25、always时序逻辑
module top_module(
input clk,
input a,
input b,
output wire out_assign,
output reg out_always_comb,
output reg out_always_ff );
assign out_assign = a^b;
always@(*)begin
out_always_comb = a^b;
end
always@(posedge clk)begin
out_always_ff <= a^b;
end
endmodule
26、IF语句
module top_module(
input a,
input b,
input sel_b1,
input sel_b2,
output wire out_assign,
output reg out_always );
assign out_assign = ((sel_b1== 1'b1) && (sel_b2 == 1'b1))? b:a;
always@(*)begin
if(sel_b1&sel_b2 == 1'b1)
out_always = b;
else out_always = a;
end
endmodule
27、if语句latches
module top_module (
input cpu_overheated,
output reg shut_off_computer,
input arrived,
input gas_tank_empty,
output reg keep_driving ); //
always @(*) begin
if (cpu_overheated)
shut_off_computer = 1;
else shut_off_computer = 0;
end
always @(*) begin
if (~arrived)
keep_driving = ~gas_tank_empty;
else keep_driving = ~arrived;
end
endmodule
28、case
// synthesis verilog_input_version verilog_2001
module top_module (
input [2:0] sel,
input [3:0] data0,
input [3:0] data1,
input [3:0] data2,
input [3:0] data3,
input [3:0] data4,
input [3:0] data5,
output reg [3:0] out );//
always@(*) begin // This is a combinational circuit
case(sel)
0:out = data0;
1:out = data1;
2:out = data2;
3:out = data3;
4:out = data4;
5:out = data5;
default:out = 'd0;
endcase
end
endmodule
29、Always nolatches
module top_module (
input [15:0] scancode,
output reg left,
output reg down,
output reg right,
output reg up );
always@(*)begin
left = 1'b0;down= 1'b0;right = 1'b0;up = 1'b0;
case(scancode)
16'he06b:left = 1'b1;
16'he072:down= 1'b1;
16'he074:right = 1'b1;
16'he075:up = 1'b1;
endcase
end
endmodule
30、Conditional ternary operator(Conditional)
module top_module (
input [7:0] a, b, c, d,
output [7:0] min);//
wire [7:0]a_b,c_d;
assign a_b = a<b? a:b;
assign c_d = c<d? c:d;
assign min = a_b<c_d? a_b:c_d;
endmodule
31、Reduction operators(Reduction)规约运算符
奇偶校验位:所有数的异或;
module top_module (
input [7:0] in,
output parity);
assign parity = ^in;
endmodule
32、population count
A “population count” circuit counts the number of '1’s in an input vector. Build a population count circuit for a 255-bit input vector.
module top_module(
input [254:0] in,
output [7:0] out );
integer i ;
always@(*)begin
out = 'b0;
for(i=0;i<255;i=i+1)begin
if(in[i] == 1'b1)
out = out +'b1;
else ;
end
end
endmodule
33、100bit全加器
module top_module(
input [99:0] a, b,
input cin,
output [99:0] cout,
output [99:0] sum );
addr add(a[0],b[0],cin,cout[0],sum[0]);
generate
genvar i;
for(i=0;i<99;i=i+1)begin:addr
addr add_i(a[i+1],b[i+1],cout[i],cout[i+1],sum[i+1]);
end
endgenerate
endmodule
module addr(
input a,b,
input cin,
output cout,
output sum
);
assign sum = a^b^cin;
assign cout = a&b | a&cin | b&cin;
endmodule
34、Bcdadd100
module top_module(
input [399:0] a, b,
input cin,
output cout,
output [399:0] sum );
wire [399:0]cout_w;
bcd_fadd bcd_fadd1(.a(a[3:0]),.b(b[3:0]),.cin(cin),.cout(cout_w[0]),.sum(sum[3:0]));
genvar i;
generate
for(i=4;i<400;i=i+4)begin:add4
bcd_fadd bcd_fadd_i(.a(a[i+3:i]),.b(b[i+3:i]),.cin(cout_w[i-4]),.cout(cout_w[i]),.sum(sum[i+3:i]));
end
endgenerate
assign cout = cout_w[396];
endmodule
35、Gates and vectors
module top_module(
input [3:0] in,
output [2:0] out_both,
output [3:1] out_any,
output [3:0] out_different );
integer i;
always@(*)begin
for(i=0;i<3;i=i+1)
out_both[i] = in[i]&in[i+1];
end
always@(*)begin
for(i=1;i<4;i=i+1)
out_any[i] = in[i]|in[i-1];
end
assign out_different = {{in[0] ^ in[3]}, {in[3] ^ in[2]}, {in[2] ^ in[1]}, {in[1] ^ in[0]}};
endmodule
36、Gates and vectors100
module top_module(
input [99:0] in,
output [98:0] out_both,
output [99:1] out_any,
output [99:0] out_different );
integer i;
always@(*)begin
for(i=0;i<99;i=i+1)
out_both[i] = in[i]&in[i+1];
end
always@(*)begin
for(i=1;i<100;i=i+1)
out_any[i] = in[i]|in[i-1];
end
assign out_different[99] = in[99]^in[0];
always@(*)begin
for(i=0;i<99;i=i+1)
out_different[i] = in[i]^in[i+1];
end
endmodule
/*或者
module top_module(
input [99:0] in,
output [98:0] out_both,
output [99:1] out_any,
output [99:0] out_different );
assign out_both = in[98:0] & in[99:1];
assign out_any = in[99:1] | in[98:0];
assign out_different = in[99:0] ^ {in[0] , in[99:1]};
endmodule
*/