瑞芯微RK3568驱动配置之十串口
瑞芯微RK3562驱动配置之十串口引脚定义rk3562-pinctrl.dtsi
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
*/
#include <dt-bindings/pinctrl/rockchip.h>
#include "rockchip-pinconf.dtsi"
/*
* This file is auto generated by pin2dts tool, please keep these code
* by adding changes at end of this file.
*/
&pinctrl {
cam {
/omit-if-no-ref/
camm0_clk0_out: camm0-clk0-out {
rockchip,pins =
/* camm0_clk0_out */
<3 RK_PB2 2 &pcfg_pull_none>;
};
/omit-if-no-ref/
camm0_clk1_out: camm0-clk1-out {
rockchip,pins =
/* camm0_clk1_out */
<3 RK_PB3 2 &pcfg_pull_none>;
};
/omit-if-no-ref/
camm1_clk0_out: camm1-clk0-out {
rockchip,pins =
/* camm1_clk0_out */
<4 RK_PB1 3 &pcfg_pull_none>;
};
/omit-if-no-ref/
camm1_clk1_out: camm1-clk1-out {
rockchip,pins =
/* camm1_clk1_out */
<4 RK_PB7 3 &pcfg_pull_none>;
};
/omit-if-no-ref/
cam_clk2_out: cam-clk2-out {
rockchip,pins =
/* cam_clk2_out */
<3 RK_PB4 2 &pcfg_pull_none>;
};
/omit-if-no-ref/
cam_clk3_out: cam-clk3-out {
rockchip,pins =
/* cam_clk3_out */
<3 RK_PB5 2 &pcfg_pull_none>;
};
};
can0 {
/omit-if-no-ref/
can0m0_pins: can0m0-pins {
rockchip,pins =
/* can0_rx_m0 */
<3 RK_PA1 4 &pcfg_pull_none>,
/* can0_tx_m0 */
<3 RK_PA0 4 &pcfg_pull_none>;
};
/omit-if-no-ref/
can0m1_pins: can0m1-pins {
rockchip,pins =
/* can0_rx_m1 */
<3 RK_PB7 6 &pcfg_pull_none>,
/* can0_tx_m1 */
<3 RK_PB6 6 &pcfg_pull_none>;
};
/omit-if-no-ref/
can0m2_pins: can0m2-pins {
rockchip,pins =
/* can0_rx_m2 */
<0 RK_PC7 2 &pcfg_pull_none>,
/* can0_tx_m2 */
<0 RK_PC6 2 &pcfg_pull_none>;
};
};
can1 {
/omit-if-no-ref/
can1m0_pins: can1m0-pins {
rockchip,pins =
/* can1_rx_m0 */
<1 RK_PB7 4 &pcfg_pull_none>,
/* can1_tx_m0 */
<1 RK_PC0 5 &pcfg_pull_none>;
};
/omit-if-no-ref/
can1m1_pins: can1m1-pins {
rockchip,pins =
/* can1_rx_m1 */
<0 RK_PC1 4 &pcfg_pull_none>,
/* can1_tx_m1 */
<0 RK_PC0 4 &pcfg_pull_none>;
};
};
clk {
/omit-if-no-ref/
clk_32k_in: clk-32k-in {
rockchip,pins =
/* clk_32k_in */
<0 RK_PB0 1 &pcfg_pull_none>;
};
};
clk0 {
/omit-if-no-ref/
clk0_32k_out: clk0-32k-out {
rockchip,pins =
/* clk0_32k_out */
<0 RK_PB0 2 &pcfg_pull_none>;
};
};
clk1 {
/omit-if-no-ref/
clk1_32k_out: clk1-32k-out {
rockchip,pins =
/* clk1_32k_out */
<2 RK_PA1 3 &pcfg_pull_none>;
};
};
cpu {
/omit-if-no-ref/
cpu_pins: cpu-pins {
rockchip,pins =
/* cpu_avs */
<0 RK_PB7 3 &pcfg_pull_none>;
};
};
dsm {
/omit-if-no-ref/
dsm_pins: dsm-pins {
rockchip,pins =
/* dsm_aud_ln */
<1 RK_PB4 5 &pcfg_pull_none>,
/* dsm_aud_lp */
<1 RK_PB3 5 &pcfg_pull_none>,
/* dsm_aud_rn */
<1 RK_PB6 6 &pcfg_pull_none>,
/* dsm_aud_rp */
<1 RK_PB5 6 &pcfg_pull_none>;
};
};
emmc {
/omit-if-no-ref/
emmc_bus8: emmc-bus8 {
rockchip,pins =
/* emmc_d0 */
<1 RK_PA0 1 &pcfg_pull_up_drv_level_2>,
/* emmc_d1 */
<1 RK_PA1 1 &pcfg_pull_up_drv_level_2>,
/* emmc_d2 */
<1 RK_PA2 1 &pcfg_pull_up_drv_level_2>,
/* emmc_d3 */
<1 RK_PA3 1 &pcfg_pull_up_drv_level_2>,
/* emmc_d4 */
<1 RK_PA4 1 &pcfg_pull_up_drv_level_2>,
/* emmc_d5 */
<1 RK_PA5 1 &pcfg_pull_up_drv_level_2>,
/* emmc_d6 */
<1 RK_PA6 1 &pcfg_pull_up_drv_level_2>,
/* emmc_d7 */
<1 RK_PA7 1 &pcfg_pull_up_drv_level_2>;
};
/omit-if-no-ref/
emmc_clk: emmc-clk {
rockchip,pins =
/* emmc_clk */
<1 RK_PB1 1 &pcfg_pull_up_drv_level_2>;
};
/omit-if-no-ref/
emmc_cmd: emmc-cmd {
rockchip,pins =
/* emmc_cmd */
<1 RK_PB0 1 &pcfg_pull_up_drv_level_2>;
};
/omit-if-no-ref/
emmc_strb: emmc-strb {
rockchip,pins =
/* emmc_strb */
<1 RK_PB2 1 &pcfg_pull_none>;
};
};
eth {
/omit-if-no-ref/
ethm0_pins: ethm0-pins {
rockchip,pins =
/* eth_clk_25m_out_m0 */
<4 RK_PB1 2 &pcfg_pull_none>;
};
/omit-if-no-ref/
ethm1_pins: ethm1-pins {
rockchip,pins =
/* eth_clk_25m_out_m1 */
<2 RK_PA1 2 &pcfg_pull_none>;
};
};
fspi {
/omit-if-no-ref/
fspi_pins: fspi-pins {
rockchip,pins =
/* fspi_clk */
<1 RK_PB1 2 &pcfg_pull_none>,
/* fspi_d0 */
<1 RK_PA0 2 &pcfg_pull_none>,
/* fspi_d1 */
<1 RK_PA1 2 &pcfg_pull_none>,
/* fspi_d2 */
<1 RK_PA2 2 &pcfg_pull_none>,
/* fspi_d3 */
<1 RK_PA3 2 &pcfg_pull_none>;
};
/omit-if-no-ref/
fspi_csn0: fspi-csn0 {
rockchip,pins =
/* fspi_csn0 */
<1 RK_PB0 2 &pcfg_pull_none>;
};
/omit-if-no-ref/
fspi_csn1: fspi-csn1 {
rockchip,pins =
/* fspi_csn1 */
<1 RK_PB2 2 &pcfg_pull_none>;
};
};
gpu {
/omit-if-no-ref/
gpu_pins: gpu-pins {
rockchip,pins =
/* gpu_avs */
<0 RK_PC0 3 &pcfg_pull_none>;
};
};
i2c0 {
/omit-if-no-ref/
i2c0_xfer: i2c0-xfer {
rockchip,pins =
/* i2c0_scl */
<0 RK_PB1 1 &pcfg_pull_none_smt>,
/* i2c0_sda */
<0 RK_PB2 1 &pcfg_pull_none_smt>;
};
};
i2c1 {
/omit-if-no-ref/
i2c1m0_xfer: i2c1m0-xfer {
rockchip,pins =
/* i2c1_scl_m0 */
<0 RK_PB3 1 &pcfg_pull_none_smt>,
/* i2c1_sda_m0 */
<0 RK_PB4 1 &pcfg_pull_none_smt>;
};
/omit-if-no-ref/
i2c1m1_xfer: i2c1m1-xfer {
rockchip,pins =
/* i2c1_scl_m1 */
<4 RK_PB4 5 &pcfg_pull_none_smt>,
/* i2c1_sda_m1 */
<4 RK_PB5 5 &pcfg_pull_none_smt>;
};
};
i2c2 {
/omit-if-no-ref/
i2c2m0_xfer: i2c2m0-xfer {
rockchip,pins =
/* i2c2_scl_m0 */
<0 RK_PB5 1 &pcfg_pull_none_smt>,
/* i2c2_sda_m0 */
<0 RK_PB6 1 &pcfg_pull_none_smt>;
};
/omit-if-no-ref/
i2c2m1_xfer: i2c2m1-xfer {
rockchip,pins =
/* i2c2_scl_m1 */
<3 RK_PD2 5 &pcfg_pull_none_smt>,
/* i2c2_sda_m1 */
<3 RK_PD3 5 &pcfg_pull_none_smt>;
};
};
i2c3 {
/omit-if-no-ref/
i2c3m0_xfer: i2c3m0-xfer {
rockchip,pins =
/* i2c3_scl_m0 */
<3 RK_PA0 1 &pcfg_pull_none_smt>,
/* i2c3_sda_m0 */
<3 RK_PA1 1 &pcfg_pull_none_smt>;
};
/omit-if-no-ref/
i2c3m1_xfer: i2c3m1-xfer {
rockchip,pins =
/* i2c3_scl_m1 */
<4 RK_PA5 5 &pcfg_pull_none_smt>,
/* i2c3_sda_m1 */
<4 RK_PA6 5 &pcfg_pull_none_smt>;
};
};
i2c4 {
/omit-if-no-ref/
i2c4m0_xfer: i2c4m0-xfer {
rockchip,pins =
/* i2c4_scl_m0 */
<3 RK_PB6 5 &pcfg_pull_none_smt>,
/* i2c4_sda_m0 */
<3 RK_PB7 5 &pcfg_pull_none_smt>;
};
/omit-if-no-ref/
i2c4m1_xfer: i2c4m1-xfer {
rockchip,pins =
/* i2c4_scl_m1 */
<0 RK_PA5 2 &pcfg_pull_none_smt>,
/* i2c4_sda_m1 */
<0 RK_PA4 2 &pcfg_pull_none_smt>;
};
};
i2c5 {
/omit-if-no-ref/
i2c5m0_xfer: i2c5m0-xfer {
rockchip,pins =
/* i2c5_scl_m0 */
<3 RK_PC2 1 &pcfg_pull_none_smt>,
/* i2c5_sda_m0 */
<3 RK_PC3 1 &pcfg_pull_none_smt>;
};
/omit-if-no-ref/
i2c5m1_xfer: i2c5m1-xfer {
rockchip,pins =
/* i2c5_scl_m1 */
<1 RK_PC7 4 &pcfg_pull_none_smt>,
/* i2c5_sda_m1 */
<1 RK_PD0 4 &pcfg_pull_none_smt>;
};
};
i2s0 {
/omit-if-no-ref/
i2s0m0_lrck: i2s0m0-lrck {
rockchip,pins =
/* i2s0_lrck_m0 */
<3 RK_PA4 1 &pcfg_pull_none_smt>;
};
/omit-if-no-ref/
i2s0m0_mclk: i2s0m0-mclk {
rockchip,pins =
/* i2s0_mclk_m0 */
<3 RK_PA2 1 &pcfg_pull_none_smt>;
};
/omit-if-no-ref/
i2s0m0_sclk: i2s0m0-sclk {
rockchip,pins =
/* i2s0_sclk_m0 */
<3 RK_PA3 1 &pcfg_pull_none_smt>;
};
/omit-if-no-ref/
i2s0m0_sdi0: i2s0m0-sdi0 {
rockchip,pins =
/* i2s0_sdi0_m0 */
<3 RK_PB1 1 &pcfg_pull_none>;
};
/omit-if-no-ref/
i2s0m0_sdi1: i2s0m0-sdi1 {
rockchip,pins =
/* i2s0_sdi1_m0 */
<3 RK_PB0 2 &pcfg_pull_none>;
};
/omit-if-no-ref/
i2s0m0_sdi2: i2s0m0-sdi2 {
rockchip,pins =
/* i2s0_sdi2_m0 */
<3 RK_PA7 2 &pcfg_pull_none>;
};
/omit-if-no-ref/
i2s0m0_sdi3: i2s0m0-sdi3 {
rockchip,pins =
/* i2s0_sdi3_m0 */
<3 RK_PA6 2 &pcfg_pull_none>;
};
/omit-if-no-ref/
i2s0m0_sdo0: i2s0m0-sdo0 {
rockchip,pins =
/* i2s0_sdo0_m0 */
<3 RK_PA5 1 &pcfg_pull_none>;
};
/omit-if-no-ref/
i2s0m0_sdo1: i2s0m0-sdo1 {
rockchip,pins =
/* i2s0_sdo1_m0 */
<3 RK_PA6 1 &pcfg_pull_none>;
};
/omit-if-no-ref/
i2s0m0_sdo2: i2s0m0-sdo2 {
rockchip,pins =
/* i2s0_sdo2_m0 */
<3 RK_PA7 1 &pcfg_pull_none>;
};
/omit-if-no-ref/
i2s0m0_sdo3: i2s0m0-sdo3 {
rockchip,pins =
/* i2s0_sdo3_m0 */
<3 RK_PB0 1 &pcfg_pull_none>;
};
/omit-if-no-ref/
i2s0m1_lrck: i2s0m1-lrck {
rockchip,pins =
/* i2s0_lrck_m1 */
<1 RK_PC4 3 &pcfg_pull_none_smt>;
};
/omit-if-no-ref/
i2s0m1_mclk: i2s0m1-mclk {
rockchip,pins =
/* i2s0_mclk_m1 */
<1 RK_PC6 3 &pcfg_pull_none_smt>;
};
/omit-if-no-ref/
i2s0m1_sclk: i2s0m1-sclk {
rockchip,pins =
/* i2s0_sclk_m1 */
<1 RK_PC5 3 &pcfg_pull_none_smt>;
};
/omit-if-no-ref/
i2s0m1_sdi0: i2s0m1-sdi0 {
rockchip,pins =
/* i2s0_sdi0_m1 */
<1 RK_PC1 3 &pcfg_pull_none>;
};
/omit-if-no-ref/
i2s0m1_sdi1: i2s0m1-sdi1 {
rockchip,pins =
/* i2s0_sdi1_m1 */
<1 RK_PC2 3 &pcfg_pull_none>;
};
/omit-if-no-ref/
i2s0m1_sdi2: i2s0m1-sdi2 {
rockchip,pins =
/* i2s0_sdi2_m1 */
<1 RK_PD3 3 &pcfg_pull_none>;
};
/omit-if-no-ref/
i2s0m1_sdi3: i2s0m1-sdi3 {
rockchip,pins =
/* i2s0_sdi3_m1 */
<1 RK_PD4 3 &pcfg_pull_none>;
};
/omit-if-no-ref/
i2s0m1_sdo0: i2s0m1-sdo0 {
rockchip,pins =
/* i2s0_sdo0_m1 */
<1 RK_PC3 3 &pcfg_pull_none>;
};
/omit-if-no-ref/
i2s0m1_sdo1: i2s0m1-sdo1 {
rockchip,pins =
/* i2s0_sdo1_m1 */
<1 RK_PD1 3 &pcfg_pull_none>;
};
/omit-if-no-ref/
i2s0m1_sdo2: i2s0m1-sdo2 {
rockchip,pins =
/* i2s0_sdo2_m1 */
<1 RK_PD2 3 &pcfg_pull_none>;
};
/omit-if-no-ref/
i2s0m1_sdo3: i2s0m1-sdo3 {
rockchip,pins =
/* i2s0_sdo3_m1 */
<2 RK_PA1 5 &pcfg_pull_none>;
};
};
i2s1 {
/omit-if-no-ref/
i2s1m0_lrck: i2s1m0-lrck {
rockchip,pins =
/* i2s1_lrck_m0 */
<3 RK_PC6 2 &pcfg_pull_none_smt>;
};
/omit-if-no-ref/
i2s1m0_mclk: i2s1m0-mclk {
rockchip,pins =
/* i2s1_mclk_m0 */
<3 RK_PC4 2 &pcfg_pull_none_smt>;
};
/omit-if-no-ref/
i2s1m0_sclk: i2s1m0-sclk {
rockchip,pins =
/* i2s1_sclk_m0 */
<3 RK_PC5 2 &pcfg_pull_none_smt>;
};
/omit-if-no-ref/
i2s1m0_sdi0: i2s1m0-sdi0 {
rockchip,pins =
/* i2s1_sdi0_m0 */
<3 RK_PD0 2 &pcfg_pull_none>;
};
/omit-if-no-ref/
i2s1m0_sdi1: i2s1m0-sdi1 {
rockchip,pins =
/* i2s1_sdi1_m0 */
<3 RK_PD1 2 &pcfg_pull_none>;
};
/omit-if-no-ref/
i2s1m0_sdi2: i2s1m0-sdi2 {
rockchip,pins =
/* i2s1_sdi2_m0 */
<3 RK_PD2 2 &pcfg_pull_none>;
};
/omit-if-no-ref/
i2s1m0_sdi3: i2s1m0-sdi3 {
rockchip,pins =
/* i2s1_sdi3_m0 */
<3 RK_PD3 2 &pcfg_pull_none>;
};
/omit-if-no-ref/
i2s1m0_sdo0: i2s1m0-sdo0 {
rockchip,pins =
/* i2s1_sdo0_m0 */
<3 RK_PC7 2 &pcfg_pull_none>;
};
/omit-if-no-ref/
i2s1m0_sdo1: i2s1m0-sdo1 {
rockchip,pins =
/* i2s1_sdo1_m0 */
<4 RK_PB4 2 &pcfg_pull_none>;
};
/omit-if-no-ref/
i2s1m0_sdo2: i2s1m0-sdo2 {
rockchip,pins =
/* i2s1_sdo2_m0 */
<4 RK_PB5 2 &pcfg_pull_none>;
};
/omit-if-no-ref/
i2s1m0_sdo3: i2s1m0-sdo3 {
rockchip,pins =
/* i2s1_sdo3_m0 */
<4 RK_PB6 2 &pcfg_pull_none>;
};
/omit-if-no-ref/
i2s1m1_lrck: i2s1m1-lrck {
rockchip,pins =
/* i2s1_lrck_m1 */
<3 RK_PB4 1 &pcfg_pull_none_smt>;
};
/omit-if-no-ref/
i2s1m1_mclk: i2s1m1-mclk {
rockchip,pins =
/* i2s1_mclk_m1 */
<3 RK_PB2 1 &pcfg_pull_none_smt>;
};
/omit-if-no-ref/
i2s1m1_sclk: i2s1m1-sclk {
rockchip,pins =
/* i2s1_sclk_m1 */
<3 RK_PB3 1 &pcfg_pull_none_smt>;
};
/omit-if-no-ref/
i2s1m1_sdi0: i2s1m1-sdi0 {
rockchip,pins =
/* i2s1_sdi0_m1 */
<3 RK_PC1 1 &pcfg_pull_none>;
};
/omit-if-no-ref/
i2s1m1_sdi1: i2s1m1-sdi1 {
rockchip,pins =
/* i2s1_sdi1_m1 */
<3 RK_PC0 2 &pcfg_pull_none>;
};
/omit-if-no-ref/
i2s1m1_sdi2: i2s1m1-sdi2 {
rockchip,pins =
/* i2s1_sdi2_m1 */
<3 RK_PB7 2 &pcfg_pull_none>;
};
/omit-if-no-ref/
i2s1m1_sdi3: i2s1m1-sdi3 {
rockchip,pins =
/* i2s1_sdi3_m1 */
<3 RK_PB6 2 &pcfg_pull_none>;
};
/omit-if-no-ref/
i2s1m1_sdo0: i2s1m1-sdo0 {
rockchip,pins =
/* i2s1_sdo0_m1 */
<3 RK_PB5 1 &pcfg_pull_none>;
};
/omit-if-no-ref/
i2s1m1_sdo1: i2s1m1-sdo1 {
rockchip,pins =
/* i2s1_sdo1_m1 */
<3 RK_PB6 1 &pcfg_pull_none>;
};
/omit-if-no-ref/
i2s1m1_sdo2: i2s1m1-sdo2 {
rockchip,pins =
/* i2s1_sdo2_m1 */
<3 RK_PB7 1 &pcfg_pull_none>;
};
/omit-if-no-ref/
i2s1m1_sdo3: i2s1m1-sdo3 {
rockchip,pins =
/* i2s1_sdo3_m1 */
<3 RK_PC0 1 &pcfg_pull_none>;
};
};
i2s2 {
/omit-if-no-ref/
i2s2m0_lrck: i2s2m0-lrck {
rockchip,pins =
/* i2s2_lrck_m0 */
<1 RK_PD6 1 &pcfg_pull_none_smt>;
};
/omit-if-no-ref/
i2s2m0_mclk: i2s2m0-mclk {
rockchip,pins =
/* i2s2_mclk_m0 */
<2 RK_PA1 1 &pcfg_pull_none_smt>;
};
/omit-if-no-ref/
i2s2m0_sclk: i2s2m0-sclk {
rockchip,pins =
/* i2s2_sclk_m0 */
<1 RK_PD5 1 &pcfg_pull_none_smt>;
};
/omit-if-no-ref/
i2s2m0_sdi: i2s2m0-sdi {
rockchip,pins =
/* i2s2_sdi_m0 */
<2 RK_PA0 1 &pcfg_pull_none>;
};
/omit-if-no-ref/
i2s2m0_sdo: i2s2m0-sdo {
rockchip,pins =
/* i2s2_sdo_m0 */
<1 RK_PD7 1 &pcfg_pull_none>;
};
/omit-if-no-ref/
i2s2m1_lrck: i2s2m1-lrck {
rockchip,pins =
/* i2s2_lrck_m1 */
<4 RK_PA1 3 &pcfg_pull_none_smt>;
};
/omit-if-no-ref/
i2s2m1_mclk: i2s2m1-mclk {
rockchip,pins =
/* i2s2_mclk_m1 */
<3 RK_PD6 3 &pcfg_pull_none_smt>;
};
/omit-if-no-ref/
i2s2m1_sclk: i2s2m1-sclk {
rockchip,pins =
/* i2s2_sclk_m1 */
<4 RK_PB1 4 &pcfg_pull_none_smt>;
};
/omit-if-no-ref/
i2s2m1_sdi: i2s2m1-sdi {
rockchip,pins =
/* i2s2_sdi_m1 */
<3 RK_PD4 4 &pcfg_pull_none>;
};
/omit-if-no-ref/
i2s2m1_sdo: i2s2m1-sdo {
rockchip,pins =
/* i2s2_sdo_m1 */
<3 RK_PD5 4 &pcfg_pull_none>;
};
};
isp {
/omit-if-no-ref/
isp_pins: isp-pins {
rockchip,pins =
/* isp_flash_trigin */
<3 RK_PC1 2 &pcfg_pull_none>,
/* isp_flash_trigout */
<3 RK_PC3 2 &pcfg_pull_none>,
/* isp_prelight_trigout */
<3 RK_PC2 2 &pcfg_pull_none>;
};
};
jtag {
/omit-if-no-ref/
jtagm0_pins: jtagm0-pins {
rockchip,pins =
/* jtag_cpu_mcu_tck_m0 */
<0 RK_PD1 2 &pcfg_pull_none>,
/* jtag_cpu_mcu_tms_m0 */
<0 RK_PD0 2 &pcfg_pull_none>;
};
/omit-if-no-ref/
jtagm1_pins: jtagm1-pins {
rockchip,pins =
/* jtag_cpu_mcu_tck_m1 */
<1 RK_PB5 2 &pcfg_pull_none>,
/* jtag_cpu_mcu_tms_m1 */
<1 RK_PB6 2 &pcfg_pull_none>;
};
};
npu {
/omit-if-no-ref/
npu_pins: npu-pins {
rockchip,pins =
/* npu_avs */
<0 RK_PC1 3 &pcfg_pull_none>;
};
};
pcie20 {
/omit-if-no-ref/
pcie20m0_pins: pcie20m0-pins {
rockchip,pins =
/* pcie20_clkreqn_m0 */
<0 RK_PA6 1 &pcfg_pull_none>,
/* pcie20_perstn_m0 */
<0 RK_PB5 2 &pcfg_pull_none>,
/* pcie20_waken_m0 */
<0 RK_PB6 2 &pcfg_pull_none>;
};
/omit-if-no-ref/
pcie20m1_pins: pcie20m1-pins {
rockchip,pins =
/* pcie20_clkreqn_m1 */
<3 RK_PA6 4 &pcfg_pull_none>,
/* pcie20_perstn_m1 */
<3 RK_PB0 4 &pcfg_pull_none>,
/* pcie20_waken_m1 */
<3 RK_PA7 4 &pcfg_pull_none>;
};
/omit-if-no-ref/
pcie20_buttonrstn: pcie20-buttonrstn {
rockchip,pins =
/* pcie20_buttonrstn */
<0 RK_PB0 3 &pcfg_pull_none>;
};
};
pdm {
/omit-if-no-ref/
pdmm0_clk0: pdmm0-clk0 {
rockchip,pins =
/* pdm_clk0_m0 */
<3 RK_PA6 3 &pcfg_pull_none>;
};
/omit-if-no-ref/
pdmm0_clk1: pdmm0-clk1 {
rockchip,pins =
/* pdm_clk1_m0 */
<3 RK_PA2 3 &pcfg_pull_none>;
};
/omit-if-no-ref/
pdmm0_sdi0: pdmm0-sdi0 {
rockchip,pins =
/* pdm_sdi0_m0 */
<3 RK_PB1 2 &pcfg_pull_none>;
};
/omit-if-no-ref/
pdmm0_sdi1: pdmm0-sdi1 {
rockchip,pins =
/* pdm_sdi1_m0 */
<3 RK_PB0 3 &pcfg_pull_none>;
};
/omit-if-no-ref/
pdmm0_sdi2: pdmm0-sdi2 {
rockchip,pins =
/* pdm_sdi2_m0 */
<3 RK_PA7 3 &pcfg_pull_none>;
};
/omit-if-no-ref/
pdmm0_sdi3: pdmm0-sdi3 {
rockchip,pins =
/* pdm_sdi3_m0 */
<3 RK_PA0 3 &pcfg_pull_none>;
};
/omit-if-no-ref/
pdmm1_clk0: pdmm1-clk0 {
rockchip,pins =
/* pdm_clk0_m1 */
<4 RK_PB7 4 &pcfg_pull_none>;
};
/omit-if-no-ref/
pdmm1_clk1: pdmm1-clk1 {
rockchip,pins =
/* pdm_clk1_m1 */
<4 RK_PB1 5 &pcfg_pull_none>;
};
/omit-if-no-ref/
pdmm1_sdi0: pdmm1-sdi0 {
rockchip,pins =
/* pdm_sdi0_m1 */
<4 RK_PA7 4 &pcfg_pull_none>;
};
/omit-if-no-ref/
pdmm1_sdi1: pdmm1-sdi1 {
rockchip,pins =
/* pdm_sdi1_m1 */
<4 RK_PB0 4 &pcfg_pull_none>;
};
/omit-if-no-ref/
pdmm1_sdi2: pdmm1-sdi2 {
rockchip,pins =
/* pdm_sdi2_m1 */
<4 RK_PA5 4 &pcfg_pull_none>;
};
/omit-if-no-ref/
pdmm1_sdi3: pdmm1-sdi3 {
rockchip,pins =
/* pdm_sdi3_m1 */
<4 RK_PA6 4 &pcfg_pull_none>;
};
};
pmic {
/omit-if-no-ref/
pmic_int: pmic-int {
rockchip,pins =
<0 RK_PA3 0 &pcfg_pull_up>;
};
/omit-if-no-ref/
soc_slppin_gpio: soc-slppin-gpio {
rockchip,pins =
<0 RK_PA2 0 &pcfg_output_low>;
};
/omit-if-no-ref/
soc_slppin_slp: soc-slppin-slp {
rockchip,pins =
<0 RK_PA2 1 &pcfg_pull_none>;
};
};
pmu {
/omit-if-no-ref/
pmu_pins: pmu-pins {
rockchip,pins =
/* pmu_debug */
<0 RK_PA5 3 &pcfg_pull_none>;
};
};
pwm0 {
/omit-if-no-ref/
pwm0m0_pins: pwm0m0-pins {
rockchip,pins =
/* pwm0_m0 */
<0 RK_PC3 2 &pcfg_pull_none_drv_level_1>;
};
/omit-if-no-ref/
pwm0m1_pins: pwm0m1-pins {
rockchip,pins =
/* pwm0_m1 */
<1 RK_PC5 4 &pcfg_pull_none_drv_level_1>;
};
};
pwm1 {
/omit-if-no-ref/
pwm1m0_pins: pwm1m0-pins {
rockchip,pins =
/* pwm1_m0 */
<0 RK_PC4 2 &pcfg_pull_none_drv_level_1>;
};
/omit-if-no-ref/
pwm1m1_pins: pwm1m1-pins {
rockchip,pins =
/* pwm1_m1 */
<1 RK_PC6 4 &pcfg_pull_none_drv_level_1>;
};
};
pwm2 {
/omit-if-no-ref/
pwm2m0_pins: pwm2m0-pins {
rockchip,pins =
/* pwm2_m0 */
<0 RK_PC5 2 &pcfg_pull_none_drv_level_1>;
};
/omit-if-no-ref/
pwm2m1_pins: pwm2m1-pins {
rockchip,pins =
/* pwm2_m1 */
<1 RK_PC7 3 &pcfg_pull_none_drv_level_1>;
};
};
pwm3 {
/omit-if-no-ref/
pwm3m0_pins: pwm3m0-pins {
rockchip,pins =
/* pwm3_m0 */
<0 RK_PA7 1 &pcfg_pull_none_drv_level_1>;
};
/omit-if-no-ref/
pwm3m1_pins: pwm3m1-pins {
rockchip,pins =
/* pwm3_m1 */
<1 RK_PD0 3 &pcfg_pull_none_drv_level_1>;
};
};
pwm4 {
/omit-if-no-ref/
pwm4m0_pins: pwm4m0-pins {
rockchip,pins =
/* pwm4_m0 */
<0 RK_PB7 2 &pcfg_pull_none_drv_level_1>;
};
/omit-if-no-ref/
pwm4m1_pins: pwm4m1-pins {
rockchip,pins =
/* pwm4_m1 */
<1 RK_PD1 4 &pcfg_pull_none_drv_level_1>;
};
};
pwm5 {
/omit-if-no-ref/
pwm5m0_pins: pwm5m0-pins {
rockchip,pins =
/* pwm5_m0 */
<0 RK_PC2 2 &pcfg_pull_none_drv_level_1>;
};
/omit-if-no-ref/
pwm5m1_pins: pwm5m1-pins {
rockchip,pins =
/* pwm5_m1 */
<1 RK_PD2 4 &pcfg_pull_none_drv_level_1>;
};
};
pwm6 {
/omit-if-no-ref/
pwm6m0_pins: pwm6m0-pins {
rockchip,pins =
/* pwm6_m0 */
<0 RK_PC1 2 &pcfg_pull_none_drv_level_1>;
};
/omit-if-no-ref/
pwm6m1_pins: pwm6m1-pins {
rockchip,pins =
/* pwm6_m1 */
<1 RK_PD3 4 &pcfg_pull_none_drv_level_1>;
};
};
pwm7 {
/omit-if-no-ref/
pwm7m0_pins: pwm7m0-pins {
rockchip,pins =
/* pwm7_m0 */
<0 RK_PC0 2 &pcfg_pull_none_drv_level_1>;
};
/omit-if-no-ref/
pwm7m1_pins: pwm7m1-pins {
rockchip,pins =
/* pwm7_m1 */
<1 RK_PD4 4 &pcfg_pull_none_drv_level_1>;
};
};
pwm8 {
/omit-if-no-ref/
pwm8m0_pins: pwm8m0-pins {
rockchip,pins =
/* pwm8_m0 */
<3 RK_PA4 2 &pcfg_pull_none_drv_level_1>;
};
/omit-if-no-ref/
pwm8m1_pins: pwm8m1-pins {
rockchip,pins =
/* pwm8_m1 */
<1 RK_PC1 4 &pcfg_pull_none_drv_level_1>;
};
};
pwm9 {
/omit-if-no-ref/
pwm9m0_pins: pwm9m0-pins {
rockchip,pins =
/* pwm9_m0 */
<3 RK_PA5 2 &pcfg_pull_none_drv_level_1>;
};
/omit-if-no-ref/
pwm9m1_pins: pwm9m1-pins {
rockchip,pins =
/* pwm9_m1 */
<1 RK_PC2 4 &pcfg_pull_none_drv_level_1>;
};
};
pwm10 {
/omit-if-no-ref/
pwm10m0_pins: pwm10m0-pins {
rockchip,pins =
/* pwm10_m0 */
<1 RK_PB5 5 &pcfg_pull_none_drv_level_1>;
};
/omit-if-no-ref/
pwm10m1_pins: pwm10m1-pins {
rockchip,pins =
/* pwm10_m1 */
<1 RK_PC3 4 &pcfg_pull_none_drv_level_1>;
};
};
pwm11 {
/omit-if-no-ref/
pwm11m0_pins: pwm11m0-pins {
rockchip,pins =
/* pwm11_m0 */
<1 RK_PB6 5 &pcfg_pull_none_drv_level_1>;
};
/omit-if-no-ref/
pwm11m1_pins: pwm11m1-pins {
rockchip,pins =
/* pwm11_m1 */
<1 RK_PC4 4 &pcfg_pull_none_drv_level_1>;
};
};
pwm12 {
/omit-if-no-ref/
pwm12m0_pins: pwm12m0-pins {
rockchip,pins =
/* pwm12_m0 */
<4 RK_PA1 4 &pcfg_pull_none_drv_level_1>;
};
/omit-if-no-ref/
pwm12m1_pins: pwm12m1-pins {
rockchip,pins =
/* pwm12_m1 */
<3 RK_PB4 5 &pcfg_pull_none_drv_level_1>;
};
};
pwm13 {
/omit-if-no-ref/
pwm13m0_pins: pwm13m0-pins {
rockchip,pins =
/* pwm13_m0 */
<4 RK_PA4 3 &pcfg_pull_none_drv_level_1>;
};
/omit-if-no-ref/
pwm13m1_pins: pwm13m1-pins {
rockchip,pins =
/* pwm13_m1 */
<3 RK_PB5 5 &pcfg_pull_none_drv_level_1>;
};
};
pwm14 {
/omit-if-no-ref/
pwm14m0_pins: pwm14m0-pins {
rockchip,pins =
/* pwm14_m0 */
<3 RK_PC5 4 &pcfg_pull_none_drv_level_1>;
};
/omit-if-no-ref/
pwm14m1_pins: pwm14m1-pins {
rockchip,pins =
/* pwm14_m1 */
<1 RK_PD7 5 &pcfg_pull_none_drv_level_1>;
};
};
pwm15 {
/omit-if-no-ref/
pwm15m0_pins: pwm15m0-pins {
rockchip,pins =
/* pwm15_m0 */
<3 RK_PC6 4 &pcfg_pull_none_drv_level_1>;
};
/omit-if-no-ref/
pwm15m1_pins: pwm15m1-pins {
rockchip,pins =
/* pwm15_m1 */
<2 RK_PA0 5 &pcfg_pull_none_drv_level_1>;
};
};
pwr {
/omit-if-no-ref/
pwr_pins: pwr-pins {
rockchip,pins =
/* pwr_ctrl0 */
<0 RK_PA2 1 &pcfg_pull_none>,
/* pwr_ctrl1 */
<0 RK_PA3 1 &pcfg_pull_none>;
};
};
ref {
/omit-if-no-ref/
ref_pins: ref-pins {
rockchip,pins =
/* ref_clk_out */
<0 RK_PA0 1 &pcfg_pull_none>;
};
};
rgmii {
/omit-if-no-ref/
rgmiim0_miim: rgmiim0-miim {
rockchip,pins =
/* rgmii_mdc_m0 */
<4 RK_PB2 2 &pcfg_pull_none>,
/* rgmii_mdio_m0 */
<4 RK_PB3 2 &pcfg_pull_none>;
};
/omit-if-no-ref/
rgmiim0_rx_er: rgmiim0-rx_er {
rockchip,pins =
/* rgmii_rxer_m0 */
<4 RK_PB0 2 &pcfg_pull_none>;
};
/omit-if-no-ref/
rgmiim0_rx_bus2: rgmiim0-rx_bus2 {
rockchip,pins =
/* rgmii_rxd0_m0 */
<4 RK_PA5 2 &pcfg_pull_none>,
/* rgmii_rxd1_m0 */
<4 RK_PA6 2 &pcfg_pull_none>,
/* rgmii_rxdv_m0 */
<4 RK_PA7 2 &pcfg_pull_none>;
};
/omit-if-no-ref/
rgmiim0_tx_bus2: rgmiim0-tx_bus2 {
rockchip,pins =
/* rgmii_txd0_m0 */
<4 RK_PA2 2 &pcfg_pull_none>,
/* rgmii_txd1_m0 */
<4 RK_PA3 2 &pcfg_pull_none>,
/* rgmii_txen_m0 */
<4 RK_PA4 2 &pcfg_pull_none>;
};
/omit-if-no-ref/
rgmiim0_rgmii_clk: rgmiim0-rgmii_clk {
rockchip,pins =
/* rgmii_rxclk_m0 */
<4 RK_PA1 2 &pcfg_pull_none>,
/* rgmii_txclk_m0 */
<3 RK_PD6 2 &pcfg_pull_none>;
};
/omit-if-no-ref/
rgmiim0_rgmii_bus: rgmiim0-rgmii_bus {
rockchip,pins =
/* rgmii_rxd2_m0 */
<3 RK_PD7 2 &pcfg_pull_none>,
/* rgmii_rxd3_m0 */
<4 RK_PA0 2 &pcfg_pull_none>,
/* rgmii_txd2_m0 */
<3 RK_PD4 2 &pcfg_pull_none>,
/* rgmii_txd3_m0 */
<3 RK_PD5 2 &pcfg_pull_none>;
};
/omit-if-no-ref/
rgmiim0_clk: rgmiim0-clk {
rockchip,pins =
/* rgmiim0_clk */
<4 RK_PB7 2 &pcfg_pull_none>;
};
/omit-if-no-ref/
rgmiim1_miim: rgmiim1-miim {
rockchip,pins =
/* rgmii_mdc_m1 */
<1 RK_PC7 2 &pcfg_pull_none>,
/* rgmii_mdio_m1 */
<1 RK_PD0 2 &pcfg_pull_none>;
};
/omit-if-no-ref/
rgmiim1_rx_er: rgmiim1-rx_er {
rockchip,pins =
/* rgmii_rxer_m1 */
<2 RK_PA0 2 &pcfg_pull_none>;
};
/omit-if-no-ref/
rgmiim1_rx_bus2: rgmiim1-rx_bus2 {
rockchip,pins =
/* rgmii_rxd0_m1 */
<1 RK_PD4 2 &pcfg_pull_none>,
/* rgmii_rxd1_m1 */
<1 RK_PD7 2 &pcfg_pull_none>,
/* rgmii_rxdv_m1 */
<1 RK_PD6 2 &pcfg_pull_none>;
};
/omit-if-no-ref/
rgmiim1_tx_bus2: rgmiim1-tx_bus2 {
rockchip,pins =
/* rgmii_txd0_m1 */
<1 RK_PD1 2 &pcfg_pull_none>,
/* rgmii_txd1_m1 */
<1 RK_PD2 2 &pcfg_pull_none>,
/* rgmii_txen_m1 */
<1 RK_PD3 2 &pcfg_pull_none>;
};
/omit-if-no-ref/
rgmiim1_rgmii_clk: rgmiim1-rgmii_clk {
rockchip,pins =
/* rgmii_rxclk_m1 */
<1 RK_PC6 2 &pcfg_pull_none>,
/* rgmii_txclk_m1 */
<1 RK_PC3 2 &pcfg_pull_none>;
};
/omit-if-no-ref/
rgmiim1_rgmii_bus: rgmiim1-rgmii_bus {
rockchip,pins =
/* rgmii_rxd2_m1 */
<1 RK_PC4 2 &pcfg_pull_none>,
/* rgmii_rxd3_m1 */
<1 RK_PC5 2 &pcfg_pull_none>,
/* rgmii_txd2_m1 */
<1 RK_PC1 2 &pcfg_pull_none>,
/* rgmii_txd3_m1 */
<1 RK_PC2 2 &pcfg_pull_none>;
};
/omit-if-no-ref/
rgmiim1_clk: rgmiim1-clk {
rockchip,pins =
/* rgmiim1_clk */
<1 RK_PD5 2 &pcfg_pull_none>;
};
};
rmii {
/omit-if-no-ref/
rmii_pins: rmii-pins {
rockchip,pins =
/* rmii_clk */
<1 RK_PD5 5 &pcfg_pull_none>,
/* rmii_mdc */
<1 RK_PC7 5 &pcfg_pull_none>,
/* rmii_mdio */
<1 RK_PD0 5 &pcfg_pull_none>,
/* rmii_rxd0 */
<1 RK_PD4 5 &pcfg_pull_none>,
/* rmii_rxd1 */
<1 RK_PD7 6 &pcfg_pull_none>,
/* rmii_rxdv_crs */
<1 RK_PD6 5 &pcfg_pull_none>,
/* rmii_rxer */
<2 RK_PA0 6 &pcfg_pull_none>,
/* rmii_txd0 */
<1 RK_PD1 5 &pcfg_pull_none>,
/* rmii_txd1 */
<1 RK_PD2 5 &pcfg_pull_none>,
/* rmii_txen */
<1 RK_PD3 5 &pcfg_pull_none>;
};
};
sdmmc0 {
/omit-if-no-ref/
sdmmc0_bus4: sdmmc0-bus4 {
rockchip,pins =
/* sdmmc0_d0 */
<1 RK_PB3 1 &pcfg_pull_up_drv_level_2>,
/* sdmmc0_d1 */
<1 RK_PB4 1 &pcfg_pull_up_drv_level_2>,
/* sdmmc0_d2 */
<1 RK_PB5 1 &pcfg_pull_up_drv_level_2>,
/* sdmmc0_d3 */
<1 RK_PB6 1 &pcfg_pull_up_drv_level_2>;
};
/omit-if-no-ref/
sdmmc0_clk: sdmmc0-clk {
rockchip,pins =
/* sdmmc0_clk */
<1 RK_PC0 1 &pcfg_pull_up_drv_level_2>;
};
/omit-if-no-ref/
sdmmc0_cmd: sdmmc0-cmd {
rockchip,pins =
/* sdmmc0_cmd */
<1 RK_PB7 1 &pcfg_pull_up_drv_level_2>;
};
/omit-if-no-ref/
sdmmc0_det: sdmmc0-det {
rockchip,pins =
/* sdmmc0_detn */
<0 RK_PA4 1 &pcfg_pull_up>;
};
/omit-if-no-ref/
sdmmc0_pwren: sdmmc0-pwren {
rockchip,pins =
/* sdmmc0_pwren */
<0 RK_PA5 1 &pcfg_pull_none>;
};
};
sdmmc1 {
/omit-if-no-ref/
sdmmc1_bus4: sdmmc1-bus4 {
rockchip,pins =
/* sdmmc1_d0 */
<1 RK_PC1 1 &pcfg_pull_up_drv_level_2>,
/* sdmmc1_d1 */
<1 RK_PC2 1 &pcfg_pull_up_drv_level_2>,
/* sdmmc1_d2 */
<1 RK_PC3 1 &pcfg_pull_up_drv_level_2>,
/* sdmmc1_d3 */
<1 RK_PC4 1 &pcfg_pull_up_drv_level_2>;
};
/omit-if-no-ref/
sdmmc1_clk: sdmmc1-clk {
rockchip,pins =
/* sdmmc1_clk */
<1 RK_PC6 1 &pcfg_pull_up_drv_level_2>;
};
/omit-if-no-ref/
sdmmc1_cmd: sdmmc1-cmd {
rockchip,pins =
/* sdmmc1_cmd */
<1 RK_PC5 1 &pcfg_pull_up_drv_level_2>;
};
/omit-if-no-ref/
sdmmc1_det: sdmmc1-det {
rockchip,pins =
/* sdmmc1_detn */
<1 RK_PD0 1 &pcfg_pull_up>;
};
/omit-if-no-ref/
sdmmc1_pwren: sdmmc1-pwren {
rockchip,pins =
/* sdmmc1_pwren */
<1 RK_PC7 1 &pcfg_pull_none>;
};
};
spdif {
/omit-if-no-ref/
spdifm0_pins: spdifm0-pins {
rockchip,pins =
/* spdif_tx_m0 */
<3 RK_PA1 3 &pcfg_pull_none>;
};
/omit-if-no-ref/
spdifm1_pins: spdifm1-pins {
rockchip,pins =
/* spdif_tx_m1 */
<0 RK_PB7 4 &pcfg_pull_none>;
};
/omit-if-no-ref/
spdifm2_pins: spdifm2-pins {
rockchip,pins =
/* spdif_tx_m2 */
<1 RK_PB7 2 &pcfg_pull_none>;
};
};
spi0 {
/omit-if-no-ref/
spi0m0_pins: spi0m0-pins {
rockchip,pins =
/* spi0_clk_m0 */
<0 RK_PC3 3 &pcfg_pull_none_drv_level_3>,
/* spi0_miso_m0 */
<0 RK_PC5 3 &pcfg_pull_none_drv_level_3>,
/* spi0_mosi_m0 */
<0 RK_PC4 3 &pcfg_pull_none_drv_level_3>;
};
/omit-if-no-ref/
spi0m0_csn0: spi0m0-csn0 {
rockchip,pins =
/* spi0m0_csn0 */
<0 RK_PC2 3 &pcfg_pull_none_drv_level_3>;
};
/omit-if-no-ref/
spi0m0_csn1: spi0m0-csn1 {
rockchip,pins =
/* spi0m0_csn1 */
<0 RK_PB7 1 &pcfg_pull_none_drv_level_3>;
};
/omit-if-no-ref/
spi0m1_pins: spi0m1-pins {
rockchip,pins =
/* spi0_clk_m1 */
<3 RK_PB5 4 &pcfg_pull_none_drv_level_3>,
/* spi0_miso_m1 */
<3 RK_PC0 4 &pcfg_pull_none_drv_level_3>,
/* spi0_mosi_m1 */
<3 RK_PB4 4 &pcfg_pull_none_drv_level_3>;
};
/omit-if-no-ref/
spi0m1_csn0: spi0m1-csn0 {
rockchip,pins =
/* spi0m1_csn0 */
<3 RK_PB7 4 &pcfg_pull_none_drv_level_3>;
};
/omit-if-no-ref/
spi0m1_csn1: spi0m1-csn1 {
rockchip,pins =
/* spi0m1_csn1 */
<3 RK_PB6 4 &pcfg_pull_none_drv_level_3>;
};
};
spi1 {
/omit-if-no-ref/
spi1m0_pins: spi1m0-pins {
rockchip,pins =
/* spi1_clk_m0 */
<3 RK_PD6 4 &pcfg_pull_none_drv_level_3>,
/* spi1_miso_m0 */
<4 RK_PA3 4 &pcfg_pull_none_drv_level_3>,
/* spi1_mosi_m0 */
<4 RK_PA2 4 &pcfg_pull_none_drv_level_3>;
};
/omit-if-no-ref/
spi1m0_csn0: spi1m0-csn0 {
rockchip,pins =
/* spi1m0_csn0 */
<3 RK_PD7 4 &pcfg_pull_none_drv_level_3>;
};
/omit-if-no-ref/
spi1m0_csn1: spi1m0-csn1 {
rockchip,pins =
/* spi1m0_csn1 */
<4 RK_PA0 4 &pcfg_pull_none_drv_level_3>;
};
/omit-if-no-ref/
spi1m1_pins: spi1m1-pins {
rockchip,pins =
/* spi1_clk_m1 */
<1 RK_PC0 4 &pcfg_pull_none_drv_level_3>,
/* spi1_miso_m1 */
<1 RK_PB4 4 &pcfg_pull_none_drv_level_3>,
/* spi1_mosi_m1 */
<1 RK_PB3 4 &pcfg_pull_none_drv_level_3>;
};
/omit-if-no-ref/
spi1m1_csn0: spi1m1-csn0 {
rockchip,pins =
/* spi1m1_csn0 */
<1 RK_PB6 4 &pcfg_pull_none_drv_level_3>;
};
/omit-if-no-ref/
spi1m1_csn1: spi1m1-csn1 {
rockchip,pins =
/* spi1m1_csn1 */
<1 RK_PB5 4 &pcfg_pull_none_drv_level_3>;
};
};
spi2 {
/omit-if-no-ref/
spi2m0_pins: spi2m0-pins {
rockchip,pins =
/* spi2_clk_m0 */
<4 RK_PB6 4 &pcfg_pull_none_drv_level_3>,
/* spi2_miso_m0 */
<3 RK_PD2 4 &pcfg_pull_none_drv_level_3>,
/* spi2_mosi_m0 */
<3 RK_PD3 4 &pcfg_pull_none_drv_level_3>;
};
/omit-if-no-ref/
spi2m0_csn0: spi2m0-csn0 {
rockchip,pins =
/* spi2m0_csn0 */
<4 RK_PB5 4 &pcfg_pull_none_drv_level_3>;
};
/omit-if-no-ref/
spi2m0_csn1: spi2m0-csn1 {
rockchip,pins =
/* spi2m0_csn1 */
<4 RK_PB4 4 &pcfg_pull_none_drv_level_3>;
};
/omit-if-no-ref/
spi2m1_pins: spi2m1-pins {
rockchip,pins =
/* spi2_clk_m1 */
<2 RK_PA1 4 &pcfg_pull_none_drv_level_3>,
/* spi2_miso_m1 */
<2 RK_PA0 4 &pcfg_pull_none_drv_level_3>,
/* spi2_mosi_m1 */
<1 RK_PD7 4 &pcfg_pull_none_drv_level_3>;
};
/omit-if-no-ref/
spi2m1_csn0: spi2m1-csn0 {
rockchip,pins =
/* spi2m1_csn0 */
<1 RK_PD6 4 &pcfg_pull_none_drv_level_3>;
};
/omit-if-no-ref/
spi2m1_csn1: spi2m1-csn1 {
rockchip,pins =
/* spi2m1_csn1 */
<1 RK_PD5 4 &pcfg_pull_none_drv_level_3>;
};
};
tsadc {
/omit-if-no-ref/
tsadcm0_pins: tsadcm0-pins {
rockchip,pins =
/* tsadc_shut_m0 */
<0 RK_PA1 1 &pcfg_pull_none>;
};
/omit-if-no-ref/
tsadcm1_pins: tsadcm1-pins {
rockchip,pins =
/* tsadc_shut_m1 */
<0 RK_PA2 2 &pcfg_pull_none>;
};
/omit-if-no-ref/
tsadc_shut_org: tsadc-shut-org {
rockchip,pins =
/* tsadc_shut_org */
<0 RK_PA1 2 &pcfg_pull_none>;
};
};
uart0 {
/omit-if-no-ref/
uart0m0_xfer: uart0m0-xfer {
rockchip,pins =
/* uart0_rx_m0 */
<0 RK_PD0 1 &pcfg_pull_up>,
/* uart0_tx_m0 */
<0 RK_PD1 1 &pcfg_pull_up>;
};
/omit-if-no-ref/
uart0m1_xfer: uart0m1-xfer {
rockchip,pins =
/* uart0_rx_m1 */
<1 RK_PB3 2 &pcfg_pull_up>,
/* uart0_tx_m1 */
<1 RK_PB4 2 &pcfg_pull_up>;
};
};
uart1 {
/omit-if-no-ref/
uart1m0_xfer: uart1m0-xfer {
rockchip,pins =
/* uart1_rx_m0 */
<1 RK_PD1 1 &pcfg_pull_up>,
/* uart1_tx_m0 */
<1 RK_PD2 1 &pcfg_pull_up>;
};
/omit-if-no-ref/
uart1m0_ctsn: uart1m0-ctsn {
rockchip,pins =
/* uart1m0_ctsn */
<1 RK_PD4 1 &pcfg_pull_none>;
};
/omit-if-no-ref/
uart1m0_rtsn: uart1m0-rtsn {
rockchip,pins =
/* uart1m0_rtsn */
<1 RK_PD3 1 &pcfg_pull_none>;
};
/omit-if-no-ref/
uart1m1_xfer: uart1m1-xfer {
rockchip,pins =
/* uart1_rx_m1 */
<4 RK_PA6 3 &pcfg_pull_up>,
/* uart1_tx_m1 */
<4 RK_PA5 3 &pcfg_pull_up>;
};
/omit-if-no-ref/
uart1m1_ctsn: uart1m1-ctsn {
rockchip,pins =
/* uart1m1_ctsn */
<4 RK_PB0 3 &pcfg_pull_none>;
};
/omit-if-no-ref/
uart1m1_rtsn: uart1m1-rtsn {
rockchip,pins =
/* uart1m1_rtsn */
<4 RK_PA7 3 &pcfg_pull_none>;
};
};
uart2 {
/omit-if-no-ref/
uart2m0_xfer: uart2m0-xfer {
rockchip,pins =
/* uart2_rx_m0 */
<0 RK_PC1 1 &pcfg_pull_up>,
/* uart2_tx_m0 */
<0 RK_PC0 1 &pcfg_pull_up>;
};
/omit-if-no-ref/
uart2m0_ctsn: uart2m0-ctsn {
rockchip,pins =
/* uart2m0_ctsn */
<0 RK_PC2 1 &pcfg_pull_none>;
};
/omit-if-no-ref/
uart2m0_rtsn: uart2m0-rtsn {
rockchip,pins =
/* uart2m0_rtsn */
<0 RK_PC3 1 &pcfg_pull_none>;
};
/omit-if-no-ref/
uart2m1_xfer: uart2m1-xfer {
rockchip,pins =
/* uart2_rx_m1 */
<3 RK_PA1 2 &pcfg_pull_up>,
/* uart2_tx_m1 */
<3 RK_PA0 2 &pcfg_pull_up>;
};
/omit-if-no-ref/
uart2m1_ctsn: uart2m1-ctsn {
rockchip,pins =
/* uart2m1_ctsn */
<3 RK_PA2 2 &pcfg_pull_none>;
};
/omit-if-no-ref/
uart2m1_rtsn: uart2m1-rtsn {
rockchip,pins =
/* uart2m1_rtsn */
<3 RK_PA3 2 &pcfg_pull_none>;
};
};
uart3 {
/omit-if-no-ref/
uart3m0_xfer: uart3m0-xfer {
rockchip,pins =
/* uart3_rx_m0 */
<4 RK_PB5 6 &pcfg_pull_up>,
/* uart3_tx_m0 */
<4 RK_PB4 6 &pcfg_pull_up>;
};
/omit-if-no-ref/
uart3m0_ctsn: uart3m0-ctsn {
rockchip,pins =
/* uart3m0_ctsn */
<4 RK_PB6 3 &pcfg_pull_none>;
};
/omit-if-no-ref/
uart3m0_rtsn: uart3m0-rtsn {
rockchip,pins =
/* uart3m0_rtsn */
<3 RK_PD1 4 &pcfg_pull_none>;
};
/omit-if-no-ref/
uart3m1_xfer: uart3m1-xfer {
rockchip,pins =
/* uart3_rx_m1 */
<3 RK_PC0 3 &pcfg_pull_up>,
/* uart3_tx_m1 */
<3 RK_PB7 3 &pcfg_pull_up>;
};
/omit-if-no-ref/
uart3m1_ctsn: uart3m1-ctsn {
rockchip,pins =
/* uart3m1_ctsn */
<3 RK_PB6 3 &pcfg_pull_none>;
};
/omit-if-no-ref/
uart3m1_rtsn: uart3m1-rtsn {
rockchip,pins =
/* uart3m1_rtsn */
<3 RK_PC1 3 &pcfg_pull_none>;
};
};
uart4 {
/omit-if-no-ref/
uart4m0_xfer: uart4m0-xfer {
rockchip,pins =
/* uart4_rx_m0 */
<3 RK_PD1 3 &pcfg_pull_up>,
/* uart4_tx_m0 */
<3 RK_PD0 3 &pcfg_pull_up>;
};
/omit-if-no-ref/
uart4m0_ctsn: uart4m0-ctsn {
rockchip,pins =
/* uart4m0_ctsn */
<3 RK_PC5 3 &pcfg_pull_none>;
};
/omit-if-no-ref/
uart4m0_rtsn: uart4m0-rtsn {
rockchip,pins =
/* uart4m0_rtsn */
<3 RK_PC6 3 &pcfg_pull_none>;
};
/omit-if-no-ref/
uart4m1_xfer: uart4m1-xfer {
rockchip,pins =
/* uart4_rx_m1 */
<1 RK_PD5 3 &pcfg_pull_up>,
/* uart4_tx_m1 */
<1 RK_PD6 3 &pcfg_pull_up>;
};
/omit-if-no-ref/
uart4m1_ctsn: uart4m1-ctsn {
rockchip,pins =
/* uart4m1_ctsn */
<2 RK_PA0 3 &pcfg_pull_none>;
};
/omit-if-no-ref/
uart4m1_rtsn: uart4m1-rtsn {
rockchip,pins =
/* uart4m1_rtsn */
<1 RK_PD7 3 &pcfg_pull_none>;
};
};
uart5 {
/omit-if-no-ref/
uart5m0_xfer: uart5m0-xfer {
rockchip,pins =
/* uart5_rx_m0 */
<1 RK_PB7 3 &pcfg_pull_up>,
/* uart5_tx_m0 */
<1 RK_PC0 3 &pcfg_pull_up>;
};
/omit-if-no-ref/
uart5m0_ctsn: uart5m0-ctsn {
rockchip,pins =
/* uart5m0_ctsn */
<1 RK_PB5 3 &pcfg_pull_none>;
};
/omit-if-no-ref/
uart5m0_rtsn: uart5m0-rtsn {
rockchip,pins =
/* uart5m0_rtsn */
<1 RK_PB6 3 &pcfg_pull_none>;
};
/omit-if-no-ref/
uart5m1_xfer: uart5m1-xfer {
rockchip,pins =
/* uart5_rx_m1 */
<3 RK_PA7 5 &pcfg_pull_up>,
/* uart5_tx_m1 */
<3 RK_PA6 5 &pcfg_pull_up>;
};
/omit-if-no-ref/
uart5m1_ctsn: uart5m1-ctsn {
rockchip,pins =
/* uart5m1_ctsn */
<3 RK_PA0 5 &pcfg_pull_none>;
};
/omit-if-no-ref/
uart5m1_rtsn: uart5m1-rtsn {
rockchip,pins =
/* uart5m1_rtsn */
<3 RK_PA1 5 &pcfg_pull_none>;
};
};
uart6 {
/omit-if-no-ref/
uart6m0_xfer: uart6m0-xfer {
rockchip,pins =
/* uart6_rx_m0 */
<0 RK_PC7 1 &pcfg_pull_up>,
/* uart6_tx_m0 */
<0 RK_PC6 1 &pcfg_pull_up>;
};
/omit-if-no-ref/
uart6m0_ctsn: uart6m0-ctsn {
rockchip,pins =
/* uart6m0_ctsn */
<0 RK_PC4 1 &pcfg_pull_none>;
};
/omit-if-no-ref/
uart6m0_rtsn: uart6m0-rtsn {
rockchip,pins =
/* uart6m0_rtsn */
<0 RK_PC5 1 &pcfg_pull_none>;
};
/omit-if-no-ref/
uart6m1_xfer: uart6m1-xfer {
rockchip,pins =
/* uart6_rx_m1 */
<4 RK_PB0 5 &pcfg_pull_up>,
/* uart6_tx_m1 */
<4 RK_PA7 5 &pcfg_pull_up>;
};
/omit-if-no-ref/
uart6m1_ctsn: uart6m1-ctsn {
rockchip,pins =
/* uart6m1_ctsn */
<4 RK_PA2 3 &pcfg_pull_none>;
};
/omit-if-no-ref/
uart6m1_rtsn: uart6m1-rtsn {
rockchip,pins =
/* uart6m1_rtsn */
<4 RK_PA3 3 &pcfg_pull_none>;
};
};
uart7 {
/omit-if-no-ref/
uart7m0_xfer: uart7m0-xfer {
rockchip,pins =
/* uart7_rx_m0 */
<3 RK_PC7 3 &pcfg_pull_up>,
/* uart7_tx_m0 */
<3 RK_PC4 3 &pcfg_pull_up>;
};
/omit-if-no-ref/
uart7m0_ctsn: uart7m0-ctsn {
rockchip,pins =
/* uart7m0_ctsn */
<3 RK_PD2 3 &pcfg_pull_none>;
};
/omit-if-no-ref/
uart7m0_rtsn: uart7m0-rtsn {
rockchip,pins =
/* uart7m0_rtsn */
<3 RK_PD3 3 &pcfg_pull_none>;
};
/omit-if-no-ref/
uart7m1_xfer: uart7m1-xfer {
rockchip,pins =
/* uart7_rx_m1 */
<1 RK_PB3 3 &pcfg_pull_up>,
/* uart7_tx_m1 */
<1 RK_PB4 3 &pcfg_pull_up>;
};
};
uart8 {
/omit-if-no-ref/
uart8m0_xfer: uart8m0-xfer {
rockchip,pins =
/* uart8_rx_m0 */
<3 RK_PB3 3 &pcfg_pull_up>,
/* uart8_tx_m0 */
<3 RK_PB2 3 &pcfg_pull_up>;
};
/omit-if-no-ref/
uart8m0_ctsn: uart8m0-ctsn {
rockchip,pins =
/* uart8m0_ctsn */
<3 RK_PB4 3 &pcfg_pull_none>;
};
/omit-if-no-ref/
uart8m0_rtsn: uart8m0-rtsn {
rockchip,pins =
/* uart8m0_rtsn */
<3 RK_PB5 3 &pcfg_pull_none>;
};
/omit-if-no-ref/
uart8m1_xfer: uart8m1-xfer {
rockchip,pins =
/* uart8_rx_m1 */
<3 RK_PD5 3 &pcfg_pull_up>,
/* uart8_tx_m1 */
<3 RK_PD4 3 &pcfg_pull_up>;
};
/omit-if-no-ref/
uart8m1_ctsn: uart8m1-ctsn {
rockchip,pins =
/* uart8m1_ctsn */
<3 RK_PD7 3 &pcfg_pull_none>;
};
/omit-if-no-ref/
uart8m1_rtsn: uart8m1-rtsn {
rockchip,pins =
/* uart8m1_rtsn */
<4 RK_PA0 3 &pcfg_pull_none>;
};
};
uart9 {
/omit-if-no-ref/
uart9m0_xfer: uart9m0-xfer {
rockchip,pins =
/* uart9_rx_m0 */
<4 RK_PB3 3 &pcfg_pull_up>,
/* uart9_tx_m0 */
<4 RK_PB2 3 &pcfg_pull_up>;
};
/omit-if-no-ref/
uart9m0_ctsn: uart9m0-ctsn {
rockchip,pins =
/* uart9m0_ctsn */
<4 RK_PB4 3 &pcfg_pull_none>;
};
/omit-if-no-ref/
uart9m0_rtsn: uart9m0-rtsn {
rockchip,pins =
/* uart9m0_rtsn */
<4 RK_PB5 3 &pcfg_pull_none>;
};
/omit-if-no-ref/
uart9m1_xfer: uart9m1-xfer {
rockchip,pins =
/* uart9_rx_m1 */
<3 RK_PC3 3 &pcfg_pull_up>,
/* uart9_tx_m1 */
<3 RK_PC2 3 &pcfg_pull_up>;
};
};
vo {
/omit-if-no-ref/
vo_pins: vo-pins {
rockchip,pins =
/* vo_lcdc_clk */
<4 RK_PB7 1 &pcfg_pull_none_drv_level_4>,
/* vo_lcdc_d0 */
<4 RK_PA4 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d1 */
<4 RK_PA5 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d2 */
<4 RK_PB2 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d3 */
<3 RK_PC4 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d4 */
<3 RK_PC5 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d5 */
<3 RK_PC6 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d6 */
<3 RK_PC7 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d7 */
<3 RK_PD0 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d8 */
<4 RK_PA6 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d9 */
<4 RK_PA7 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d10 */
<3 RK_PD1 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d11 */
<3 RK_PD2 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d12 */
<3 RK_PD3 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d13 */
<3 RK_PD4 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d14 */
<3 RK_PD5 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d15 */
<3 RK_PD6 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d16 */
<4 RK_PB0 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d17 */
<4 RK_PB1 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d18 */
<4 RK_PB3 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d19 */
<3 RK_PD7 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d20 */
<4 RK_PA0 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d21 */
<4 RK_PA1 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d22 */
<4 RK_PA2 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d23 */
<4 RK_PA3 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_den */
<4 RK_PB6 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_hsync */
<4 RK_PB4 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_vsync */
<4 RK_PB5 1 &pcfg_pull_none_drv_level_3>;
};
};
};
/*
* This part is edited handly.
*/
&pinctrl {
vo {
/omit-if-no-ref/
bt1120_pins: bt1120-pins {
rockchip,pins =
/* vo_lcdc_clk */
<4 RK_PB7 1 &pcfg_pull_none_drv_level_4>,
/* vo_lcdc_d3 */
<3 RK_PC4 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d4 */
<3 RK_PC5 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d5 */
<3 RK_PC6 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d6 */
<3 RK_PC7 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d7 */
<3 RK_PD0 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d10 */
<3 RK_PD1 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d11 */
<3 RK_PD2 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d12 */
<3 RK_PD3 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d13 */
<3 RK_PD4 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d14 */
<3 RK_PD5 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d15 */
<3 RK_PD6 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d19 */
<3 RK_PD7 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d20 */
<4 RK_PA0 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d21 */
<4 RK_PA1 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d22 */
<4 RK_PA2 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d23 */
<4 RK_PA3 1 &pcfg_pull_none_drv_level_3>;
};
/omit-if-no-ref/
bt656_pins: bt656-pins {
rockchip,pins =
/* vo_lcdc_clk */
<4 RK_PB7 1 &pcfg_pull_none_drv_level_4>,
/* vo_lcdc_d3 */
<3 RK_PC4 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d4 */
<3 RK_PC5 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d5 */
<3 RK_PC6 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d6 */
<3 RK_PC7 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d7 */
<3 RK_PD0 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d10 */
<3 RK_PD1 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d11 */
<3 RK_PD2 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d12 */
<3 RK_PD3 1 &pcfg_pull_none_drv_level_3>;
};
/omit-if-no-ref/
rgb3x8_pins_m0: rgb3x8-pins-m0 {
rockchip,pins =
/* vo_lcdc_clk */
<4 RK_PB7 1 &pcfg_pull_none_drv_level_4>,
/* vo_lcdc_d3 */
<3 RK_PC4 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d4 */
<3 RK_PC5 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d5 */
<3 RK_PC6 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d6 */
<3 RK_PC7 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d7 */
<3 RK_PD0 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d10 */
<3 RK_PD1 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d11 */
<3 RK_PD2 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d12 */
<3 RK_PD3 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_den */
<4 RK_PB6 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_hsync */
<4 RK_PB4 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_vsync */
<4 RK_PB5 1 &pcfg_pull_none_drv_level_3>;
};
/omit-if-no-ref/
rgb3x8_pins_m1: rgb3x8-pins-m1 {
rockchip,pins =
/* vo_lcdc_clk */
<4 RK_PB7 1 &pcfg_pull_none_drv_level_4>,
/* vo_lcdc_d13 */
<3 RK_PD4 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d14 */
<3 RK_PD5 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d15 */
<3 RK_PD6 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d19 */
<3 RK_PD7 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d20 */
<4 RK_PA0 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d21 */
<4 RK_PA1 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d22 */
<4 RK_PA2 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d23 */
<4 RK_PA3 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_den */
<4 RK_PB6 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_hsync */
<4 RK_PB4 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_vsync */
<4 RK_PB5 1 &pcfg_pull_none_drv_level_3>;
};
/omit-if-no-ref/
rgb565_pins: rgb565-pins {
rockchip,pins =
/* vo_lcdc_clk */
<4 RK_PB7 1 &pcfg_pull_none_drv_level_4>,
/* vo_lcdc_d3 */
<3 RK_PC4 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d4 */
<3 RK_PC5 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d5 */
<3 RK_PC6 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d6 */
<3 RK_PC7 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d7 */
<3 RK_PD0 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d10 */
<3 RK_PD1 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d11 */
<3 RK_PD2 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d12 */
<3 RK_PD3 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d13 */
<3 RK_PD4 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d14 */
<3 RK_PD5 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d15 */
<3 RK_PD6 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d19 */
<3 RK_PD7 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d20 */
<4 RK_PA0 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d21 */
<4 RK_PA1 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d22 */
<4 RK_PA2 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d23 */
<4 RK_PA3 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_den */
<4 RK_PB6 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_hsync */
<4 RK_PB4 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_vsync */
<4 RK_PB5 1 &pcfg_pull_none_drv_level_3>;
};
/omit-if-no-ref/
rgb666_pins: rgb666-pins {
rockchip,pins =
/* vo_lcdc_clk */
<4 RK_PB7 1 &pcfg_pull_none_drv_level_4>,
/* vo_lcdc_d2 */
<4 RK_PB2 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d3 */
<3 RK_PC4 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d4 */
<3 RK_PC5 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d5 */
<3 RK_PC6 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d6 */
<3 RK_PC7 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d7 */
<3 RK_PD0 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d10 */
<3 RK_PD1 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d11 */
<3 RK_PD2 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d12 */
<3 RK_PD3 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d13 */
<3 RK_PD4 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d14 */
<3 RK_PD5 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d15 */
<3 RK_PD6 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d18 */
<4 RK_PB3 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d19 */
<3 RK_PD7 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d20 */
<4 RK_PA0 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d21 */
<4 RK_PA1 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d22 */
<4 RK_PA2 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d23 */
<4 RK_PA3 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_den */
<4 RK_PB6 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_hsync */
<4 RK_PB4 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_vsync */
<4 RK_PB5 1 &pcfg_pull_none_drv_level_3>;
};
};
};
Chaptet1 瑞芯微RK3568驱动配置之十串口
原文链接：https://blog.csdn.net/huntenganwei/article/details/127086202
基于飞凌的开发板设计，这里需要使用到RK3568的串口，开发板只开放了UART2、UART3、UART4、UART5、UART8。查看文档，准备配置UART0、UART6、UART7、UART9。一共9个串口使用。剩下的一个串口被网口1占用，暂时不修改。
修改设备树DTS文件配置。
地址：
/home/forlinx/3568/OK3568-linux-source/kernel/arch/arm64/boot/dts/rockchip
rk3568.dtsi为基本配置文件，只需要修改OK3568-C-common.dtsi。
占用了LVDS的管脚，LVDS无法使用。
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pwm/pwm.h>
#include <dt-bindings/input/rk-input.h>
#include <dt-bindings/display/drm_mipi_dsi.h>
#include <dt-bindings/display/rockchip_vop.h>
#include <dt-bindings/display/media-bus-format.h>
#include "rk3568.dtsi"
/ {
model = "Forlinx OK3568-C Board";
compatible = "forlinx,ok3568", "rockchip,rk3568-evb1-ddr4-v10", "rockchip,rk3568";
//only hdmi
forlinx_control {
status = "okay";
video-hdmi = "hdmi";
video-mipi-edp = "off";
video-lvds = "off";
};
edp-panel {
compatible = "simple-panel";
prepare-delay-ms = <120>;
enable-delay-ms = <120>;
unprepare-delay-ms = <120>;
disable-delay-ms = <120>;
backlight = <&edp_backlight>;
enable-gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
port {
panel_in_edp: endpoint {
remote-endpoint = <&edp_out_panel>;
};
};
};
panel {
compatible = "simple-panel";
backlight = <&lvds_backlight>;
power-supply = <&vcc3v3_lcd2_n>;
enable-delay-ms = <20>;
prepare-delay-ms = <20>;
unprepare-delay-ms = <20>;
disable-delay-ms = <20>;
bus-format = <MEDIA_BUS_FMT_RGB888_1X7X4_SPWG>;
width-mm = <152>;
height-mm = <91>;
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <71000000>;
hactive = <1280>;
vactive = <800>;
hback-porch = <10>;
hfront-porch = <140>;
vback-porch = <1>;
vfront-porch = <2>;
hsync-len = <10>;
vsync-len = <20>;
hsync-active = <0>;
vsync-active = <1>;
de-active = <1>;
pixelclk-active = <0>;
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dual-lvds-even-pixels;
panel_in_lvds: endpoint {
remote-endpoint = <&lvds_out_panel>;
};
};
};
};
adc_keys: adc-keys {
compatible = "adc-keys";
io-channels = <&saradc 0>;
io-channel-names = "buttons";
keyup-threshold-microvolt = <1800000>;
poll-interval = <100>;
vol-up-key {
label = "volume up";
linux,code = <KEY_VOLUMEUP>;
press-threshold-microvolt = <1750>;
};
vol-down-key {
label = "volume down";
linux,code = <KEY_VOLUMEDOWN>;
press-threshold-microvolt = <297500>;
};
menu-key {
label = "menu";
linux,code = <KEY_MENU>;
press-threshold-microvolt = <980000>;
};
back-key {
label = "back";
linux,code = <KEY_BACK>;
press-threshold-microvolt = <1305500>;
};
};
leds: leds {
compatible = "gpio-leds";
work_led: work {
gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
hdmi_sound: hdmi-sound {
status = "okay";
compatible = "rockchip,hdmi";
rockchip,mclk-fs = <128>;
rockchip,card-name = "rockchip,hdmi";
rockchip,cpu = <&i2s0_8ch>;
rockchip,codec = <&hdmi>;
rockchip,jack-det;
};
pdmics: dummy-codec {
status = "disabled";
compatible = "rockchip,dummy-codec";
#sound-dai-cells = <0>;
};
pdm_mic_array: pdm-mic-array {
status = "disabled";
compatible = "simple-audio-card";
simple-audio-card,name = "rockchip,pdm-mic-array";
simple-audio-card,cpu {
sound-dai = <&pdm>;
};
simple-audio-card,codec {
sound-dai = <&pdmics>;
};
};
audiopwmout_diff: audiopwmout-diff {
status = "disabled";
compatible = "simple-audio-card";
simple-audio-card,format = "i2s";
simple-audio-card,name = "rockchip,audiopwmout-diff";
simple-audio-card,mclk-fs = <256>;
simple-audio-card,bitclock-master = <&master>;
simple-audio-card,frame-master = <&master>;
simple-audio-card,cpu {
sound-dai = <&i2s3_2ch>;
};
master: simple-audio-card,codec {
sound-dai = <&dig_acodec>;
};
};
rk809_sound: rk809-sound {
status = "okay";
compatible = "simple-audio-card";
simple-audio-card,format = "i2s";
simple-audio-card,name = "rockchip,rk809-codec";
simple-audio-card,hp-det-gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
simple-audio-card,widgets = "Headphones", "Headphones Jack";
simple-audio-card,mclk-fs = <256>;
simple-audio-card,cpu {
sound-dai = <&i2s1_8ch>;
};
simple-audio-card,codec {
sound-dai = <&rk809_codec>;
};
};
spdif-sound {
status = "disabled";
compatible = "simple-audio-card";
simple-audio-card,name = "ROCKCHIP,SPDIF";
simple-audio-card,cpu {
sound-dai = <&spdif_8ch>;
};
simple-audio-card,codec {
sound-dai = <&spdif_out>;
};
};
spdif_out: spdif-out {
status = "disabled";
compatible = "linux,spdif-dit";
#sound-dai-cells = <0>;
};
vcc12v: vcc-12v {
compatible = "regulator-fixed";
regulator-name = "vcc12v";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
};
vcc5v0_sys: vcc5v0-sys {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc12v>;
};
vcc3v3_sys: vcc3v3-sys {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc5v0_sys>;
};
//for main board
vcc3v3: vcc-3v3 {
compatible = "regulator-fixed";
regulator-name = "vcc3v3";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc5v0_sys>;
};
vcc1v8: vcc-1v8 {
compatible = "regulator-fixed";
regulator-name = "vcc1v8";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vcc3v3>;
};
vcc1v2: vcc-1v2 {
compatible = "regulator-fixed";
regulator-name = "vcc1v2";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
vin-supply = <&vcc3v3>;
};
vcc2v8: vcc-2v8 {
compatible = "regulator-fixed";
regulator-name = "vcc2v8";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
vin-supply = <&vcc3v3>;
};
vcc3v3_lcd2_n: vcc3v3-lcd2-n {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_lcd2_n";
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
enable-active-high;
gpio = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
vin-supply = <&vcc3v3_sys>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
clocks = <&rk809 1>;
clock-names = "ext_clock";
pinctrl-names = "default";
pinctrl-0 = <&wifi_enable_h>;
/*
* On the module itself this is one of these (depending
* on the actual card populated):
* - SDIO_RESET_L_WL_REG_ON
* - PDN (power down when low)
*/
post-power-on-delay-ms = <200>;
reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_LOW>;
};
vcc2v5_sys: vcc2v5-ddr {
compatible = "regulator-fixed";
regulator-name = "vcc2v5-sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
vin-supply = <&vcc3v3_sys>;
};
5g-rst {
compatible = "regulator-fixed";
regulator-name = "5g-rst";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio1 RK_PB2 GPIO_ACTIVE_LOW>;
enable-active-low;
regulator-boot-on;
regulator-always-on;
pinctrl-names = "default";
pinctrl-0 = <&net_5g_rst_gpio>;
status = "okay";
};
5g-pwr {
compatible = "regulator-fixed";
regulator-name = "5g-pwr";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-boot-on;
regulator-always-on;
pinctrl-names = "default";
pinctrl-0 = <&net_5g_pwr_gpio>;
status = "okay";
};
fiq-debugger {
compatible = "rockchip,fiq-debugger";
rockchip,serial-id = <2>;
rockchip,wake-irq = <0>;
/* If enable uart uses irq instead of fiq */
rockchip,irq-mode-enable = <1>;
rockchip,baudrate = <115200>; /* Only 115200 and 1500000 */
interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&uart2m0_xfer>;
status = "okay";
};
debug: debug@fd904000 {
compatible = "rockchip,debug";
reg = <0x0 0xfd904000 0x0 0x1000>,
<0x0 0xfd905000 0x0 0x1000>,
<0x0 0xfd906000 0x0 0x1000>,
<0x0 0xfd907000 0x0 0x1000>;
};
cspmu: cspmu@fd90c000 {
compatible = "rockchip,cspmu";
reg = <0x0 0xfd90c000 0x0 0x1000>,
<0x0 0xfd90d000 0x0 0x1000>,
<0x0 0xfd90e000 0x0 0x1000>,
<0x0 0xfd90f000 0x0 0x1000>;
};
test-power {
status = "okay";
};
rk_headset: rk-headset {
status = "disabled";
compatible = "rockchip_headset";
headset_gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&hp_det>;
io-channels = <&saradc 2>;
};
dsi1_backlight: dsi1-backlight {
compatible = "pwm-backlight";
pwms = <&pwm5 0 20000 0>;
brightness-levels = <
0 20 20 21 21 22 22 23
23 24 24 25 25 26 26 27
27 28 28 29 29 30 30 31
31 32 32 33 33 34 34 35
35 36 36 37 37 38 38 39
40 41 42 43 44 45 46 47
48 49 50 51 52 53 54 55
56 57 58 59 60 61 62 63
64 65 66 67 68 69 70 71
72 73 74 75 76 77 78 79
80 81 82 83 84 85 86 87
88 89 90 91 92 93 94 95
96 97 98 99 100 101 102 103
104 105 106 107 108 109 110 111
112 113 114 115 116 117 118 119
120 121 122 123 124 125 126 127
128 129 130 131 132 133 134 135
136 137 138 139 140 141 142 143
144 145 146 147 148 149 150 151
152 153 154 155 156 157 158 159
160 161 162 163 164 165 166 167
168 169 170 171 172 173 174 175
176 177 178 179 180 181 182 183
184 185 186 187 188 189 190 191
192 193 194 195 196 197 198 199
200 201 202 203 204 205 206 207
208 209 210 211 212 213 214 215
216 217 218 219 220 221 222 223
224 225 226 227 228 229 230 231
232 233 234 235 236 237 238 239
240 241 242 243 244 245 246 247
248 249 250 251 252 253 254 255
>;
default-brightness-level = <200>;
is-forlinx;
};
lvds_backlight: lvds-backlight {
compatible = "pwm-backlight";
pwms = <&pwm14 0 20000 0>;
brightness-levels = <
0 20 20 21 21 22 22 23
23 24 24 25 25 26 26 27
27 28 28 29 29 30 30 31
31 32 32 33 33 34 34 35
35 36 36 37 37 38 38 39
40 41 42 43 44 45 46 47
48 49 50 51 52 53 54 55
56 57 58 59 60 61 62 63
64 65 66 67 68 69 70 71
72 73 74 75 76 77 78 79
80 81 82 83 84 85 86 87
88 89 90 91 92 93 94 95
96 97 98 99 100 101 102 103
104 105 106 107 108 109 110 111
112 113 114 115 116 117 118 119
120 121 122 123 124 125 126 127
128 129 130 131 132 133 134 135
136 137 138 139 140 141 142 143
144 145 146 147 148 149 150 151
152 153 154 155 156 157 158 159
160 161 162 163 164 165 166 167
168 169 170 171 172 173 174 175
176 177 178 179 180 181 182 183
184 185 186 187 188 189 190 191
192 193 194 195 196 197 198 199
200 201 202 203 204 205 206 207
208 209 210 211 212 213 214 215
216 217 218 219 220 221 222 223
224 225 226 227 228 229 230 231
232 233 234 235 236 237 238 239
240 241 242 243 244 245 246 247
248 249 250 251 252 253 254 255
>;
default-brightness-level = <200>;
is-forlinx;
};
edp_backlight: edp-backlight {
compatible = "pwm-backlight";
pwms = <&pwm3 0 20000 0>;
brightness-levels = <
0 20 20 21 21 22 22 23
23 24 24 25 25 26 26 27
27 28 28 29 29 30 30 31
31 32 32 33 33 34 34 35
35 36 36 37 37 38 38 39
40 41 42 43 44 45 46 47
48 49 50 51 52 53 54 55
56 57 58 59 60 61 62 63
64 65 66 67 68 69 70 71
72 73 74 75 76 77 78 79
80 81 82 83 84 85 86 87
88 89 90 91 92 93 94 95
96 97 98 99 100 101 102 103
104 105 106 107 108 109 110 111
112 113 114 115 116 117 118 119
120 121 122 123 124 125 126 127
128 129 130 131 132 133 134 135
136 137 138 139 140 141 142 143
144 145 146 147 148 149 150 151
152 153 154 155 156 157 158 159
160 161 162 163 164 165 166 167
168 169 170 171 172 173 174 175
176 177 178 179 180 181 182 183
184 185 186 187 188 189 190 191
192 193 194 195 196 197 198 199
200 201 202 203 204 205 206 207
208 209 210 211 212 213 214 215
216 217 218 219 220 221 222 223
224 225 226 227 228 229 230 231
232 233 234 235 236 237 238 239
240 241 242 243 244 245 246 247
248 249 250 251 252 253 254 255
>;
default-brightness-level = <200>;
};
};
&reserved_memory {
ramoops: ramoops@110000 {
compatible = "ramoops";
reg = <0x0 0x110000 0x0 0xf0000>;
record-size = <0x20000>;
console-size = <0x80000>;
ftrace-size = <0x00000>;
pmsg-size = <0x50000>;
};
};
&rng {
status = "okay";
};
&rockchip_suspend {
status = "okay";
};
&combphy0_us {
status = "okay";
};
&combphy1_usq {
status = "okay";
};
&combphy2_psq {
status = "okay";
};
&csi2_dphy_hw {
status = "okay";
};
&csi2_dphy0 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi_in_ov13850: endpoint@1 {
reg = <1>;
remote-endpoint = <&ov13850_out>;
data-lanes = <1 2>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
csidphy_out: endpoint@0 {
reg = <0>;
remote-endpoint = <&isp0_in>;
};
};
};
};
&gmac0 {
phy-mode = "rgmii";
clock_in_out = "output";
snps,reset-gpio = <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
/* Reset time is 20ms, 100ms for rtl8211f */
snps,reset-delays-us = <0 20000 100000>;
assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>, <&cru CLK_MAC0_OUT>;
assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
assigned-clock-rates = <0>, <125000000>, <25000000>;
pinctrl-names = "default";
pinctrl-0 = <&gmac0_miim
&gmac0_tx_bus2
&gmac0_rx_bus2
&gmac0_rgmii_clk
&gmac0_rgmii_bus
ð0_pins>;
tx_delay = <0x2f>;
rx_delay = <0x00>;
phy-handle = <&rgmii_phy0>;
status = "okay";
};
&gmac1 {
phy-mode = "rgmii";
clock_in_out = "output";
snps,reset-gpio = <&gpio3 RK_PA2 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
/* Reset time is 20ms, 100ms for rtl8211f */
snps,reset-delays-us = <0 20000 100000>;
assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>, <&cru CLK_MAC1_OUT>;
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
assigned-clock-rates = <0>, <125000000>, <25000000>;
pinctrl-names = "default";
pinctrl-0 = <&gmac1m1_miim
&gmac1m1_tx_bus2
&gmac1m1_rx_bus2
&gmac1m1_rgmii_clk
&gmac1m1_rgmii_bus
ð1m1_pins>;
tx_delay = <0x35>;
rx_delay = <0x00>;
phy-handle = <&rgmii_phy1>;
status = "okay";
};
&mdio0 {
rgmii_phy0: phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x0>;
clocks = <&cru CLK_MAC0_OUT>;
};
};
&mdio1 {
rgmii_phy1: phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x0>;
clocks = <&cru CLK_MAC1_OUT>;
};
};
&video_phy0 {
status = "disabled";
};
&video_phy1 {
status = "disabled";
};
/*
&pcie30phy {
status = "okay";
};
&pcie3x2 {
reset-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
enable-gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_sys>;
status = "okay";
};
&pcie2x1 {
reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_sys>;
status = "okay";
};
*/
&pinctrl {
touch {
touch_gpio: touch-gpio {
rockchip,pins =
<1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>,
<1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
};
ft5x06_int: ft5x06-int {
rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>,
<0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>;
};
dsi_gt911_int: dsi-gt911-int {
rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>,
<0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
cam {
camera_pwr: camera-pwr {
rockchip,pins =
/* camera power en */
<0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
};
ov13850_default_pin: ov13850-default-pin {
rockchip,pins =
<4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>,
<0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
};
ov13850_sleep_pin: ov13850-sleep-pin {
rockchip,pins =
<4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>,
<0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
headphone {
hp_det: hp-det {
rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pmic {
pmic_int: pmic_int {
rockchip,pins =
<0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
};
soc_slppin_gpio: soc_slppin_gpio {
rockchip,pins =
<0 RK_PA2 RK_FUNC_GPIO &pcfg_output_low_pull_down>;
};
soc_slppin_slp: soc_slppin_slp {
rockchip,pins =
<0 RK_PA2 1 &pcfg_pull_up>;
};
soc_slppin_rst: soc_slppin_rst {
rockchip,pins =
<0 RK_PA2 2 &pcfg_pull_none>;
};
};
sdio-pwrseq {
wifi_enable_h: wifi-enable-h {
rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
5g {
net_5g_rst_gpio: net_5g_rst_gpio {
rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
};
net_5g_pwr_gpio: net_5g_pwr_gpio {
rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&rkisp {
status = "okay";
};
&rkisp_mmu {
status = "okay";
};
&rkisp_vir0 {
status = "okay";
port {
#address-cells = <1>;
#size-cells = <0>;
isp0_in: endpoint@0 {
reg = <0>;
remote-endpoint = <&csidphy_out>;
};
};
};
&sdmmc2 {
max-frequency = <150000000>;
supports-sdio;
bus-width = <4>;
disable-wp;
cap-sd-highspeed;
cap-sdio-irq;
keep-power-in-suspend;
mmc-pwrseq = <&sdio_pwrseq>;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>;
sd-uhs-sdr104;
status = "okay";
};
&uart8 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart8m0_xfer &uart8m0_ctsn &uart8m0_rtsn>;
};
&bus_npu {
bus-supply = <&vdd_logic>;
pvtm-supply = <&vdd_cpu>;
status = "okay";
};
&can0 {
assigned-clocks = <&cru CLK_CAN0>;
assigned-clock-rates = <200000000>;
pinctrl-names = "default";
pinctrl-0 = <&can0m0_pins>;
status = "okay";
};
&can1 {
assigned-clocks = <&cru CLK_CAN1>;
assigned-clock-rates = <200000000>;
pinctrl-names = "default";
pinctrl-0 = <&can1m1_pins>;
status = "okay";
};
&can2 {
assigned-clocks = <&cru CLK_CAN2>;
assigned-clock-rates = <150000000>;
pinctrl-names = "default";
pinctrl-0 = <&can2m1_pins>;
status = "disabled";
};
&cpu0 {
cpu-supply = <&vdd_cpu>;
};
&dfi {
status = "okay";
};
&dmc {
center-supply = <&vdd_logic>;
status = "okay";
};
&gpu {
mali-supply = <&vdd_gpu>;
status = "okay";
};
&i2c0 {
status = "okay";
vdd_cpu: tcs4525@1c {
compatible = "tcs,tcs452x";
reg = <0x1c>;
vin-supply = <&vcc5v0_sys>;
regulator-compatible = "fan53555-reg";
regulator-name = "vdd_cpu";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1390000>;
regulator-init-microvolt = <900000>;
regulator-ramp-delay = <2300>;
fcs,suspend-voltage-selector = <1>;
regulator-boot-on;
regulator-always-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
rk809: pmic@20 {
compatible = "rockchip,rk809";
reg = <0x20>;
interrupt-parent = <&gpio0>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default", "pmic-sleep",
"pmic-power-off", "pmic-reset";
pinctrl-0 = <&pmic_int>;
pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>;
pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>;
pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>;
rockchip,system-power-controller;
wakeup-source;
#clock-cells = <1>;
clock-output-names = "rk808-clkout1", "rk808-clkout2";
//fb-inner-reg-idxs = <2>;
/* 1: rst regs (default in codes), 0: rst the pmic */
pmic-reset-func = <0>;
/* not save the PMIC_POWER_EN register in uboot */
not-save-power-en = <1>;
vcc1-supply = <&vcc3v3_sys>;
vcc2-supply = <&vcc3v3_sys>;
vcc3-supply = <&vcc3v3_sys>;
vcc4-supply = <&vcc3v3_sys>;
vcc5-supply = <&vcc3v3_sys>;
vcc6-supply = <&vcc3v3_sys>;
vcc7-supply = <&vcc3v3_sys>;
vcc8-supply = <&vcc3v3_sys>;
vcc9-supply = <&vcc3v3_sys>;
pwrkey {
status = "okay";
};
pinctrl_rk8xx: pinctrl_rk8xx {
gpio-controller;
#gpio-cells = <2>;
rk817_slppin_null: rk817_slppin_null {
pins = "gpio_slp";
function = "pin_fun0";
};
rk817_slppin_slp: rk817_slppin_slp {
pins = "gpio_slp";
function = "pin_fun1";
};
rk817_slppin_pwrdn: rk817_slppin_pwrdn {
pins = "gpio_slp";
function = "pin_fun2";
};
rk817_slppin_rst: rk817_slppin_rst {
pins = "gpio_slp";
function = "pin_fun3";
};
};
regulators {
vdd_logic: DCDC_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-init-microvolt = <900000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>;
regulator-name = "vdd_logic";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_gpu: DCDC_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-init-microvolt = <900000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>;
regulator-name = "vdd_gpu";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_ddr: DCDC_REG3 {
regulator-always-on;
regulator-boot-on;
regulator-initial-mode = <0x2>;
regulator-name = "vcc_ddr";
regulator-state-mem {
regulator-on-in-suspend;
};
};
vdd_npu: DCDC_REG4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-init-microvolt = <900000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>;
regulator-name = "vdd_npu";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdda0v9_image: LDO_REG1 {
regulator-boot-on;
regulator-always-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-name = "vdda0v9_image";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdda_0v9: LDO_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-name = "vdda_0v9";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdda0v9_pmu: LDO_REG3 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-name = "vdda0v9_pmu";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <900000>;
};
};
vccio_acodec: LDO_REG4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vccio_acodec";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vccio_sd: LDO_REG5 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vccio_sd";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc3v3_pmu: LDO_REG6 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc3v3_pmu";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcca_1v8: LDO_REG7 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcca_1v8";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcca1v8_pmu: LDO_REG8 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcca1v8_pmu";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vcca1v8_image: LDO_REG9 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcca1v8_image";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_1v8: DCDC_REG5 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc_1v8";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_3v3: SWITCH_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc_3v3";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc3v3_sd: SWITCH_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc3v3_sd";
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
rk809_codec: codec {
#sound-dai-cells = <0>;
compatible = "rockchip,rk809-codec", "rockchip,rk817-codec";
clocks = <&cru I2S1_MCLKOUT>;
clock-names = "mclk";
assigned-clocks = <&cru I2S1_MCLKOUT>, <&cru I2S1_MCLK_TX_IOE>;
assigned-clock-rates = <12288000>;
assigned-clock-parents = <&cru I2S1_MCLKOUT_TX>, <&cru I2S1_MCLKOUT_TX>;
pinctrl-names = "default";
pinctrl-0 = <&i2s1m0_mclk>;
hp-volume = <20>;
spk-volume = <3>;
mic-in-differential;
status = "okay";
};
};
};
&i2c2 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c2m1_xfer>;
vm149c_0: vm149c@0c {
compatible = "silicon touch,vm149c";
status = "okay";
reg = <0x0c>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
};
ov13850: ov13850@10 {
compatible = "ovti,ov13850";
status = "okay";
reg = <0x10>;
clocks = <&cru CLK_CIF_OUT>;
clock-names = "xvclk";
power-domains = <&power RK3568_PD_VI>;
pinctrl-names = "default";
pinctrl-0 = <&cif_clk>, <&ov13850_default_pin>;
pwdn-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "ov13850-csi";
rockchip,camera-module-lens-name = "ov13850-2mp";
lens-focus = <&vm149c_0>;
port {
ov13850_out: endpoint {
remote-endpoint = <&mipi_in_ov13850>;
data-lanes = <1 2>;
};
};
};
gt9xx_lvds: gt9xx@5d {
compatible = "goodix,gt928";
reg = <0x5d>;
pinctrl-names = "default";
pinctrl-0 = <&touch_gpio>;
interrupt-parent = <&gpio1>;
interrupts = <RK_PA4 IRQ_TYPE_EDGE_FALLING>;
irq-gpio = <&gpio1 RK_PA4 IRQ_TYPE_LEVEL_LOW>;
reset-gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>;
touchscreen-size-x = <1280>;
touchscreen-size-y = <800>;
touchscreen-swapped-x-y;
uniq = "lvds";
status = "okay";
};
gt9xx_dsi: gt9xx@14 {
compatible = "goodix,gt928";
reg = <0x14>;
pinctrl-names = "default";
pinctrl-0 = <&dsi_gt911_int>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PA0 IRQ_TYPE_EDGE_FALLING>;
irq-gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
reset-gpio = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>;
touchscreen-size-x = <1024>;
touchscreen-size-y = <600>;
uniq = "dsi";
status = "okay";
};
polytouch: edt-ft5x06@38{
compatible = "edt,edt-ft5406", "edt,edt-ft5x06";
reg = <0x38>;
pinctrl-names = "defaults";
pinctrl-0 = <&ft5x06_int>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PA0 IRQ_TYPE_EDGE_FALLING>;
touchscreen-size-x = <1024>;
touchscreen-size-y = <600>;
status = "okay";
};
};
&i2c3 {
status = "okay";
rx8010: rx8010@32 {
compatible = "epson,rx8010";
reg = <0x32>;
};
pcf8563: pcf8563@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
#clock-cells = <0>;
};
};
&i2s0_8ch {
status = "okay";
};
&i2s1_8ch {
status = "okay";
rockchip,clk-trcm = <1>;
pinctrl-names = "default";
pinctrl-0 = <&i2s1m0_sclktx
&i2s1m0_lrcktx
&i2s1m0_sdi0
&i2s1m0_sdo0>;
};
&iep {
status = "okay";
};
&iep_mmu {
status = "okay";
};
&jpegd {
status = "okay";
};
&jpegd_mmu {
status = "okay";
};
&mpp_srv {
status = "okay";
};
&nandc0 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
nand@0 {
reg = <0>;
nand-bus-width = <8>;
nand-ecc-mode = "hw";
nand-ecc-strength = <16>;
nand-ecc-step-size = <1024>;
};
};
/*
* There are 10 independent IO domains in RK3566/RK3568, including PMUIO[0:2] and VCCIO[1:7].
* 1/ PMUIO0 and PMUIO1 are fixed-level power domains which cannot be configured;
* 2/ PMUIO2 and VCCIO1,VCCIO[3:7] domains require that their hardware power supply voltages
* must be consistent with the software configuration correspondingly
* a/ When the hardware IO level is connected to 1.8V, the software voltage configuration
* should also be configured to 1.8V accordingly;
* b/ When the hardware IO level is connected to 3.3V, the software voltage configuration
* should also be configured to 3.3V accordingly;
* 3/ VCCIO2 voltage control selection (0xFDC20140)
* BIT[0]: 0x0: from GPIO_0A7 (default)
* BIT[0]: 0x1: from GRF
* Default is determined by Pin FLASH_VOL_SEL/GPIO0_A7:
* L:VCCIO2 must supply 3.3V
* H:VCCIO2 must supply 1.8V
*/
&pmu_io_domains {
status = "okay";
pmuio1-supply = <&vcc3v3_pmu>;
pmuio2-supply = <&vcc3v3_pmu>;
vccio1-supply = <&vccio_acodec>;
vccio3-supply = <&vccio_sd>;
vccio4-supply = <&vcc_1v8>;
vccio5-supply = <&vcc_3v3>;
vccio6-supply = <&vcc_1v8>;
vccio7-supply = <&vcc_3v3>;
};
&pwm3 {
status = "okay";
};
&pwm5 {
status = "okay";
};
&pwm14 {
status = "disabled";
};
&rk_rga {
status = "okay";
};
&rkvdec {
status = "okay";
};
&rkvdec_mmu {
status = "okay";
};
&rkvenc {
venc-supply = <&vdd_logic>;
status = "okay";
};
&rkvenc_mmu {
status = "okay";
};
&rknpu {
rknpu-supply = <&vdd_npu>;
status = "okay";
};
&rknpu_mmu {
status = "okay";
};
&saradc {
status = "okay";
vref-supply = <&vcca_1v8>;
};
&sdhci {
bus-width = <8>;
supports-emmc;
non-removable;
max-frequency = <200000000>;
status = "okay";
};
&sdmmc0 {
max-frequency = <150000000>;
supports-sd;
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
disable-wp;
sd-uhs-sdr104;
vmmc-supply = <&vcc3v3_sd>;
vqmmc-supply = <&vccio_sd>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
//20220927 by gan
status = "disabled";
};
&sfc {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&fspi_pins>;
flash: m25p80@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spansion,m25p80", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <40000000>;
m25p,fast-read;
};
};
&spdif_8ch {
status = "disabled";
pinctrl-names = "default";
pinctrl-0 = <&spdifm1_tx>;
};
&tsadc {
status = "okay";
};
&u2phy0_host {
status = "okay";
};
&u2phy0_otg {
status = "okay";
};
&u2phy1_host {
status = "okay";
};
&u2phy1_otg {
status = "okay";
};
&usb2phy0 {
status = "okay";
};
&usb2phy1 {
status = "okay";
};
&usb_host0_ehci {
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};
&usb_host1_ehci {
status = "okay";
};
&usb_host1_ohci {
status = "okay";
};
&usbdrd_dwc3 {
dr_mode = "otg";
extcon = <&usb2phy0>;
status = "okay";
};
&usbdrd30 {
status = "okay";
};
&usbhost_dwc3 {
status = "okay";
};
&usbhost30 {
status = "okay";
};
&vad {
rockchip,audio-src = <&i2s1_8ch>;
rockchip,buffer-time-ms = <128>;
rockchip,det-channel = <0>;
rockchip,mode = <0>;
};
&vdpu {
status = "okay";
};
&vdpu_mmu {
status = "okay";
};
&vepu {
status = "okay";
};
&vepu_mmu {
status = "okay";
};
&vop {
status = "okay";
assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>, <&cru DCLK_VOP2>;
assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>, <&cru PLL_GPLL>;
disable-win-move;
};
&vop_mmu {
status = "okay";
};
&vp0 {
cursor-win-id = <ROCKCHIP_VOP2_CLUSTER0>;
};
&vp1 {
cursor-win-id = <ROCKCHIP_VOP2_CLUSTER1>;
};
&edp {
status = "disabled";
pinctrl-names = "default";
pinctrl-0 = <&edpdpm0_pins>;
ports {
port@1 {
reg = <1>;
edp_out_panel: endpoint {
remote-endpoint = <&panel_in_edp>;
};
};
};
};
&edp_phy {
status = "disabled";
};
&edp_in_vp0 {
status = "disabled";
};
&edp_in_vp1 {
status = "disabled";
};
&route_edp {
status = "disabled";
connect = <&vp1_out_edp>;
};
&route_dsi1 {
status = "disabled";
connect = <&vp1_out_dsi1>;
};
&dsi1_in_vp0 {
status = "disabled";
};
&dsi1_in_vp1 {
status = "disabled";
};
&dsi1 {
status = "disabled";
//rockchip,lane-rate = <1000>;
dsi1_panel: panel@0 {
status = "okay";
compatible = "simple-panel-dsi";
reg = <0>;
reset-delay-ms = <60>;
enable-delay-ms = <60>;
prepare-delay-ms = <60>;
unprepare-delay-ms = <60>;
disable-delay-ms = <60>;
dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>;
dsi,format = <MIPI_DSI_FMT_RGB888>;
dsi,lanes = <4>;
panel-init-sequence = [
];
panel-exit-sequence = [
];
panel-width-mm = <68>;
panel-height-mm = <121>;
backlight = <&dsi1_backlight>;
enable-gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>;
display-timings {
native-mode = <&panel7_1024x600>;
panel7_1024x600: timings {
hback-porch = <48>;
hfront-porch = <40>;
hactive = <1024>;
hsync-len = <48>;
vback-porch = <48>;
vfront-porch = <40>;
vactive = <600>;
vsync-len = <4>;
clock-frequency = <45000000>;
vsync-active = <0>;
hsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
panel_in_dsi: endpoint {
remote-endpoint = <&dsi_out_panel>;
};
};
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
dsi_out_panel: endpoint {
remote-endpoint = <&panel_in_dsi>;
};
};
};
};
&hdmi {
status = "disabled";
rockchip,phy-table =
<92812500 0x8009 0x0000 0x0270>,
<165000000 0x800b 0x0000 0x026d>,
<185625000 0x800b 0x0000 0x01ed>,
<297000000 0x800b 0x0000 0x01ad>,
<594000000 0x8029 0x0000 0x0088>,
<000000000 0x0000 0x0000 0x0000>;
};
&hdmi_in_vp0 {
status = "disabled";
};
&hdmi_in_vp1 {
status = "disabled";
};
&route_hdmi {
status = "disabled";
connect = <&vp0_out_hdmi>;
};
&lvds {
status = "disabled";
phys = <&video_phy0>;
phy-names = "phy";
ports {
port@1 {
reg = <1>;
lvds_out_panel: endpoint {
remote-endpoint = <&panel_in_lvds>;
};
};
};
};
&lvds_in_vp1 {
status = "disabled";
};
&lvds_in_vp2 {
status = "disabled";
};
&route_lvds {
status = "disabled";
connect = <&vp2_out_lvds>;
};
&xin32k {
status = "disabled";
};
&uart3 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart3m1_xfer>;
};
&uart4 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart4m1_xfer>;
};
&uart5 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart5m1_xfer>;
};
/
&uart0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart0_xfer>;
};
&uart6 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart6m1_xfer>;
};
&uart7 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart7m1_xfer>;
};
&uart9 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart9m1_xfer>;
};
//
&spi0 {
pinctrl-names = "default", "high_speed";
pinctrl-0 = <&spi0m1_cs0 &spi0m1_pins>;
pinctrl-1 = <&spi0m1_cs0 &spi0m1_pins_hs>;
status = "disabled";
spi@0 {
compatible = "rockchip,spidev";
reg = <0>;
spi-max-frequency = <50000000>;
};
};
&spi2 {
pinctrl-names = "default", "high_speed";
pinctrl-0 = <&spi2m1_cs0 &spi2m1_cs1 &spi2m1_pins>;
pinctrl-1 = <&spi2m1_cs0 &spi2m1_cs1 &spi2m1_pins_hs>;
status = "okay";
spi@0 {
compatible = "rockchip,spidev";
reg = <0>;
spi-max-frequency = <50000000>;
};
spi@1 {
compatible = "rockchip,spidev";
reg = <1>;
spi-max-frequency = <50000000>;
};
};
Chapter2 创龙瑞芯微RK3568设备树1（修改设备树GPIO和串口）
原文链接：https://blog.csdn.net/weixin_45426095/article/details/135214400
前言
最近一直在搞3568的东西，涉及到底层的设备树修改，驱动编写等等，忙的焦头烂额的，也没时间往下面写东西了。今天差不多底层的东西快弄完了，把最近的感悟给大家分享下，并且加入点设备树的基础知识。给刚刚涉足开发板学习的小伙伴一点帮助。当然对于大神们来说，写的肯定是皮毛。一起共勉！
基础
涉及到的知识，我会用类比的方法和STM32的硬件做对比，其实弄完之后发现两个差不多，没有什么本质的区别。所以小伙伴看之前的基础是必须编写过单片机的程序，对单片机的架构有一定的了解，要不看完会更迷茫。
题外话
学习这个真是很痛苦，并且不知道自己做的对不对，需要一遍一遍的测试。并且问了其他小伙伴，有一个共同的感觉：随着年龄的增加，学习能力大大下降。并且已经抽不出那么多精力去学习能力了。
每天刷抖音，看到什么35岁失业什么的，其实吧，感觉有三个原因吧，仅仅是自己猜测：
（1）技术没有做扎实就转到管理岗了。公司发展太快，所以刚进去的技术还没有很好的基础，就转到管理，使得自己的技术不扎实，再从管理岗转回来，已经很难了。
（2）技术也不错，但是忘记了学习，一直做自己习惯的东西，然后到了管理。但是到了管理之后，技术更新了，以前的技术已经适应不了现在的东西了。这个应该是大部分人的问题吧。就算在一个技术上做的时间长了，也会不学习了，感觉现在的东西够了。当然学习新的东西会很难、很闹心。其实我也想一直做单片机，也就控制几个灯，控制几个外设。然后搞搞逻辑啥的。一直在自己的舒适区。
（3）技术也够，学习也一直在学，但是换个工作工资低了，不愿将就。但愿每个人都是因为这个原因。
内容
这次介绍4个内容，都是最简单的外设：（1）GPIO，（2）串口，（3）I2C，（4）CAN。这4个应该能包含大部分硬件应用了，当然还有麻烦的，后面再慢慢介绍，一点一点的来。先介绍最基本的，大概有个印象。
1.GPIO
GPIO_InitTypeDef GPIO_Initure;
__HAL_RCC_GPIOE_CLK_ENABLE();
GPIO_Initure.Pin = GPIO_PIN_15;
GPIO_Initure.Mode = GPIO_MODE_INPUT;
GPIO_Initure.Pull = GPIO_PULLUP;
GPIO_Initure.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
HAL_GPIO_Init(GPIOE, &GPIO_Initure);
这个是单片机的GPIO初始化。定义GPIO结构体，开时钟，管脚号，管脚输入，管脚模式，管脚速度，参数传入结构体。
HAL_GPIO_WritePin(GPIOE, GPIO_PIN_9, GPIO_PIN_SET);
这个是控制程序。直接根据HALk库给的函数就行。要是不用HAL库，自己控制，也都是别人给好的API函数。
对比下来，在Linux的3568设备树里：
gpioled1 {
compatible = "MY,led1";
led1-gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
status = "okay";
};
先说第二句：gpio的管脚定义，第三句：状态定义。
第一句是匹配定义，这个后面再说。后面牵涉到驱动部分，这个后面会详细介绍，所以现在先由个概念，知道是这么回事。
至此到这里，GPIO的设备树部分介绍完毕。下面说下两者的区别，仅仅说对于GPIO设定部分的区别哈，其他的就不说了，没啥用。
相同点：定义了管脚，并且定义了初始电平；
不同点：单片机定义了管脚的输入和输出，3568定义了匹配字。至于语法的区别，就不做过多的介绍了。
所以，3568里面还需要对其他的进行定义，第一个：输入输出定义，第二个：控制程序。这个后面再说。先说下，输入输出定义在驱动里面定义，控制程序也是线程的API，只要拿过来使用就行了。
2.串口
GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Alternate = GPIO_AF7_USART2;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
先说第一部分，管脚定义。这部分应该很熟悉，定义管脚，定义管脚复用，然后定义复用到什么上面，然后参数传入结构体。这部分是管脚的定义。
huart2.Instance = USART2;
huart2.Init.BaudRate = 1000000;
huart2.Init.WordLength = UART_WORDLENGTH_8B;
huart2.Init.StopBits = UART_STOPBITS_1;
huart2.Init.Parity = UART_PARITY_NONE;
huart2.Init.Mode = UART_MODE_TX_RX;
HAL_UART_Init(&huart2);
然后说第二部分，串口定义。前面定义了管脚，相当于管脚已经复用到了串口上，然后定义串口的信息。对应串口2，波特率，起始位，停止位等。
HAL_NVIC_SetPriority(USART2_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(USART2_IRQn);
然后就是中断函数，接收和发送中断。对应的就是接收和发送函数中断。这个API在it.c里面应该可以找到。要是找不到就直接去库函数里面找。
对比下来，在3568的设备树里：
uart1 {
/omit-if-no-ref/
uart1m0_xfer: uart1m0-xfer {
rockchip,pins =
/* uart1_rxm0 */
<2 RK_PB3 2 &pcfg_pull_up>,
/* uart1_txm0 */
<2 RK_PB4 2 &pcfg_pull_up>;
};
/omit-if-no-ref/
uart1m0_ctsn: uart1m0-ctsn {
rockchip,pins =
/* uart1m0_ctsn */
<2 RK_PB6 2 &pcfg_pull_none>;
};
/omit-if-no-ref/
uart1m0_rtsn: uart1m0-rtsn {
rockchip,pins =
/* uart1m0_rtsn */
<2 RK_PB5 2 &pcfg_pull_none>;
};
/omit-if-no-ref/
uart1m1_xfer: uart1m1-xfer {
rockchip,pins =
/* uart1_rxm1 */
<3 RK_PD7 4 &pcfg_pull_up>,
/* uart1_txm1 */
<3 RK_PD6 4 &pcfg_pull_up>;
};
/omit-if-no-ref/
uart1m1_ctsn: uart1m1-ctsn {
rockchip,pins =
/* uart1m1_ctsn */
<4 RK_PC1 4 &pcfg_pull_none>;
};
/omit-if-no-ref/
uart1m1_rtsn: uart1m1-rtsn {
rockchip,pins =
/* uart1m1_rtsn */
<4 RK_PB6 4 &pcfg_pull_none>;
};
};
这个是pinctrl里面的设备树结构。里面包含串口的各种复用管脚定义。里面m0和m1可以自己选择，当然选择方法在后面。
对比不同点：单片机里面直接写出来用哪个管脚，用哪个需要自己去写。而3568里面全部给你写出来，然后你自己再配置。
uart1: serial@fe650000 {
compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
reg = <0x0 0xfe650000 0x0 0x100>;
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
dmas = <&dmac0 2>, <&dmac0 3>;
pinctrl-names = "default";
pinctrl-0 = <&uart1m0_xfer>;
status = "disabled";
};
然后底层的设备树，这部分不用修改，别人给写好的。至于怎么写，不用管，只知道在这里就行。
解释下：匹配字，状态，寄存器地址。中断地址，时钟，时钟名称，寄存器偏移，寄存器宽度，DMA，管脚名称，管脚初始定义。
其实在单片机里，中断函数已经给你配好了，而设备树里直接给你写出来了。怎么写的 ，千万别去研究，别人做好的，直接用就行，或者直接知道是啥东西就行。然后管脚选用的是m0。这个是别人的初始定义，后面可以再修改。所以这个地方就看看，知道是啥就行，至于reg啥的，千万别管。
&uart1 {
status = "okay";
pinctrl-0 = <&uart1m1_xfer>;
};
这是后面的自己定义。前面别人给个初始的，后面用不用看自己。用的话就来个okay，不用就不用管。要是用的话，管脚不一样咋弄，那就给改改。
然后，然后就没了。就那么多东西。
对于GPIO中的驱动，GPIO的驱动简单，可以自己写一个。但是串口的比较麻烦，别人都写好了，不用管。配好设备树之后，linux会自己加载驱动函数。就像单片机里面的收发中断，然后放到buffer里面。其实你也不知道咋驱动的，就是可以收到数，然后解析就行。
切记：千万别深究，千万别深究。
不同
设备树放的比较乱，如果别人开发的不好，放的会更乱，所以选开发板的时候选大厂的。放的位置好，你就好看点，学习起来也快。至于程序放的位置，放哪都行，随你意，但是最好按照别人写好的去放，看起来方便。
单片机里面的东西，都是一块一块的，相对来说，别人都给你封好了，3568或者其他开发板里面的程序都是按照功能一大块放一起，看起来比较麻烦。
总结
设备树就是将单片机的不同的功能，大家放一起，然后自己挑出来。并且用很晦涩的表达方式表达出来，不用看懂具体是啥，也不用纠结怎么去编写，会改管脚就行。给的pdf里面肯定会有说明怎么弄，要是没有，引用别人的话：赶紧跑路，还搞啥，自己肯定编不了。
后续
接触的时候脑袋疼，这是啥，这又是啥。当真的去一个一个的琢磨之后，才发现，哦，和单片机差不多。学习顺序：克服心理障碍，静下心，一句一句的看，不会的查，改，改，改，不用担心改错，反正也改不坏。还有一定要做好备份，在修改任何东西前，一定先保存一份，万一改错了还能复原，再从开始改。
后面介绍I2C和CAN的设备树，然后再介绍GPIO的驱动函数，然后就再ETH，然后再其他的。慢慢来。喜欢的小伙伴点个关注，后续文章继续发送。
Chapter3 QT串口大量数据动态实时显示（三）========“customplot绘图步骤”
原文链接：https://blog.csdn.net/weixin_45426095/article/details/110261931
前言
在《QT串口动态实时显示大量数据波形曲线（一）》和《QT串口动态实时显示大量数据波形曲线（二）》中介绍了串口编程和chart绘图编程。也介绍了chart和customplot绘图的基本区别。customplot绘图在代码上非常简单，不用点，线，坐标系和图表一层一层的放那么麻烦。
第一部分： 串口接收大量数据动态显示的难点
串口大量数据QT接收时问题的原因：
（1）10ms40个8位数。在示波器上监视串口波形，其实这个总线负载率差不多到了60%。如果再想传输更多的数据，只能利用更高的波特率，但是119200差不多是最高的波特率了，更高的只能自己去编写代码，比较麻烦。将总线负载率进一步升高。底层的传输机制不太允许（底层芯片的DMA传输已经用上），传输数据太多容易引起错误码。
（2）上层串口接收机制不完善，也就是《一》中介绍的串口接收readyread函数和readall函数的问题，所以传输数据不能进一步增加。进一步增加之后接收中断（暂时这样叫吧）次数也随之增加，影响绘图时间，同时接收的数据会出现丢点现象，这一点我在试验时验证过，接收数据太多就会丢点。
（3）接收数据多之后，绘图就会增加。数据点增加不会大幅度增加时间，但是增加图表数量会增加程序执行时间，对串口的接收造成影响。这一点也经过验证。
选择customplot绘图的原因：
（1）程序简单，（2）图表多种多样，好看，（3）手势程序简单（观察波形时使用）
Chapter4 创龙瑞芯微RK3568参数修改（调试口波特率和rootfs文件，串口波特率默认：1500000bps，建议修改为115200bps）
前言
前面写了基本的文件编译、系统编译和系统烧写，差不多前期工作就准备的差不多了。目前的东西能解决大部分入门级的需求。当然如果需要开发的话，还需要修改其他东西，下面一步一步的给小伙伴介绍关键参数怎么修改。
给定波特率
拿到开发板的时候，按照给的文档一步一步的来，达到烧写系统的程度并不是很难，但是调试的时候又遇到了问题。第一个就是连接调试串口的时候，这个挺麻烦。
串口波特率：1500000。
连接的软件：SecureCRT 7.3，必须用这个，其他的试过，好像都出不来，没办法，只能用跟这个，给的软件里面有，可以直接安装。
进去之后按照步骤去改就行，至于怎么设置，这个就不多介绍了，很多网页都可以搜到。唯一需要告诉的就是1500000怎么设置。开始的很迷茫，串口波特率都是选择的，咋有1500000呢？
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