状态机专题练习

根据以下描述功能用verilog编写一段代码，并用状态机来实现该功能

(1）状态机：实现一个测试过程，该过程包括启动准备状态、启动测试、停止测试、查询测试结果、显示测试结果、测试结束返回初始化6个状态；用时间来控制该过程，90秒内完成该过程
（2）描述状态跳转时间；
（3）编码实现

参考思路

代码

由于计数器设置的是90计数，我在case中设置的是60s结束，所以后面30s 4个LED灯常亮（主要是懒的再拍一遍视频）

module qrs(
	input	wire		clk,	//1秒震荡50_000_000次，周期是20ns
	input	wire		rst_n,	//1s = 1_000_000_000ns,震荡一次是20ns，
	
	output	reg	[3:0]	led
);

reg	[32:0]	cnt;
reg   [1:0]    cstate;

localparam s0_on = 0;
localparam s1_on = 1;
localparam s2_on = 2;
localparam s3_on = 3;
localparam s4_on = 4;
localparam s5_on = 5;

//计数器模块
always@(posedge clk or negedge rst_n)begin
	if(!rst_n)							//按下复位键
		cnt <= 0;						//计数清零
	else if(cnt == 33'd4_500_000_000 - 1)	//计数达到最大值
		cnt <= 1'b0;						//计数清零
	else						
		cnt <= cnt + 1'b1;				//否则计数自增1
end


always @(posedge clk or negedge rst_n)begin
if(!rst_n)
    begin
	      cstate<=s0_on;
			led<=4'b1111;
	 end
else
    case(cstate)
	      s0_on : begin
			                 led<=4'b1111;
								  if(cnt==50_000_000 -1) //50_000_000为1s
								       cstate <=s1_on;
									else
									    cstate <=cstate;
							end
							
	      s1_on : begin
			                 led<=4'b0001;
								  if(cnt==1_050_000_000 -1) //21s
								       cstate <=s2_on;
									else
									    cstate <=cstate;
							end

	      s2_on : begin
			                 led<=4'b0010;
								  if(cnt==2_550_000_000 -1) //51s
								       cstate <=s3_on;
									else
									    cstate <=cstate;
							end

	      s3_on : begin
			                 led<=4'b0100;
								  if(cnt==2_600_000_000 -1)//52s
								       cstate <=s4_on;
									else
									    cstate <=cstate;
							end

	      s4_on : begin
			                 led<=4'b11000;
								  if(cnt==2_750_000_000 -1)//55s
								       cstate <=s5_on;
									else
									    cstate <=cstate;
							end

	      s5_on : begin
			                 led<=4'b1111;
								  if(cnt==3_000_000_000 -1)//60s
								       cstate <=s0_on;
									else
									    cstate <=cstate;
							end
			
			default : begin
			                 led<=4'b0000;
								  if(cnt==50_000_000 -1)
								       cstate <=s1_on;
									else
									    cstate <=cstate;
							end

	endcase

end

endmodule							
							

视频效果

嵌入式FPGA状态机练习1

画出可以检测10010串的状态图, 并用verilog编程实现

思路

代码实现

module qrs(  //输入输出端口定义
	input wire clk,
	input wire rst_n,
	input wire cin,
	
	output reg[3:0] led

);
	
	//内部寄存器及连线定义
	reg [2:0] curr_state;
	reg [2:0] next_state;
	
	//状态编码
	parameter idle = 3'b000;
	parameter s1 = 3'b001;
	parameter s2 = 3'b010;
	parameter s3 = 3'b011;
	parameter s4 = 3'b100;

	//状态机实现
	always@(posedge clk or negedge rst_n)
	begin
		if(!rst_n) 
			curr_state <= idle;
		else
			curr_state <= next_state;
	end
			
	always@(posedge clk or negedge rst_n)
		begin
			case(curr_state)
				idle: begin
						if(cin == 1) begin 
							next_state <= s1;
							led <= 4'b0000;
						
						end

						else next_state <= idle;
					  end
				s1: begin
						if(cin == 0) begin 
						   next_state <= s2;
							led <= 4'b0001;
						end
						  
						else next_state <= s1;
					end
					
				
				s2: begin
						if(cin == 0) begin 
						   next_state <= s3;
							led <= 4'b0011;
						end
						  
						else next_state <= s2;
					end
				s3: begin
						if(cin == 1) begin 
						   next_state <= s4;
							led <= 4'b0111;
						end
						
						else next_state <= 3;
					end
				s4:	begin
						if(cin == 0) 
						begin
							next_state <= idle;
							led <= 4'b1111;
						end
						else next_state <= s4;
					end
				default: next_state <= idle;
			endcase
		end
endmodule			

视频

FPGA专题训练2

参考

FPGA工程师笔试面试题（四）-爱代码爱编程