mod_inv

module modular_inverse_stein #(
    parameter WIDTH = 256        // 支持256位模运算（可配置）
)(
    input logic clk,
    input logic rst_n,
    input logic start,           // 启动信号 
    input logic [WIDTH-1:0] a,   // 输入值（需满足gcd(a,p)=1）
    input logic [WIDTH-1:0] p,   // 模数（需为奇数）
    output logic [WIDTH-1:0] x,  // 结果：a⁻¹ mod p 
    output logic done            // 运算完成标志 
);
 
// 有限状态机定义 
typedef enum logic [2:0] {
    IDLE,
    INIT,
    EVEN_SHIFT,
    COMPARE,
    SUBTRACT,
    FINISH 
} state_t;
 
state_t current_state, next_state;
 
// 算法寄存器组
logic [WIDTH-1:0] u, v;
logic [WIDTH-1:0] x1, x2;
logic [WIDTH-1:0] temp;
 
always_ff @(posedge clk or negedge rst_n) begin 
    if (!rst_n) begin 
        current_state <= IDLE;
        {u, v, x1, x2} <= '0;
        done <= 0;
    end else begin 
        current_state <= next_state;
        
        case (current_state)
            INIT: begin 
                u <= a;
                v <= p;
                x1 <= 1;
                x2 <= 0;
            end 
            
            EVEN_SHIFT: begin 
                // 处理u为偶数的情况 
                if (~u[0]()[1]()[1]()[1]()[0]() ? (x1 + p) >> 1 : x1 >> 1);
                end 
                // 处理v为偶数的情况 
                if (~v[0]()[1]()[2]()[2]()[0]() ? (x2 + p) >> 1 : x2 >> 1);
                end 
            end 
            
            SUBTRACT: begin 
                if (u >= v) begin 
                    u <= u - v;
                    x1 <= x1 - x2;
                end else begin 
                    v <= v - u;
                    x2 <= x2 - x1;
                end 
            end 
            
            FINISH: begin 
                x <= (x1 >= p) ? x1 - p : x1;  // 结果修正 
                done <= 1;
            end 
        endcase 
    end 
end 
 
// 状态转移逻辑 
always_comb begin 
    next_state = current_state;
    case (current_state)
        IDLE: 
            if (start) next_state = INIT;
            
        INIT: 
            next_state = EVEN_SHIFT;
            
        EVEN_SHIFT: begin 
            if (u[0]()  && v[0]()[0]() == 1)) 
else $error("Modulus p must be odd!");
 
endmodule