状态机任意编码计数器

用状态机设计任意编码计数器，实现如下编码 7 进制计数器： 0 ， 2 ， 5 ， 3 ， 4 ， 6 ， 1 ， 并通过数码管显示。

div模块：

module div(clk,divi_clk1);
input clk;
output reg divi_clk1;
reg [31:0] count_reg;
always@(posedge clk)
begin
if(count_reg==32'd24999999)
begin
divi_clk1<=~divi_clk1;
count_reg<=32'd0;
end
else
begin
count_reg<=count_reg+32'd1;
end
end
endmodule
fsm7模块：

module fsm7(clk,rst,cq);
input clk,rst;
output reg [3:0]cq;
parameter [2:0]s1=3'b000,s2=3'b010,s3=3'b101,s4=3'b011,s5=3'b100,s6=3'b110,s7=3'b001;
reg [2:0]current,next;
always@(posedge clk or negedge rst)
begin 
if(!rst)
current<=s1;
else current<=next;
end
always@(current)
begin 
case(current)
s1:begin
     cq<=s1;
     next<=s2;
     end
s2:begin
     cq<=s2;
     next<=s3;
     end
s3:begin
     cq<=s3;
     next<=s4;
     end
s4:begin
     cq<=s4;
     next<=s5;
     end
s5:begin
     cq<=s5;
     next<=s6;
     end 
s6:begin
     cq<=s6;
     next<=s7;
     end 
s7:begin
     cq<=s7;
     next<=s1;
     end 
default:begin
      cq<=s1;
      next<=s1;
      end
      endcase
end
endmodule 

seg模块：

module seg(d_in,a,b,c,d,e,f,g,dp,ds);
input[3:0] d_in;
output ds;
output a,b,c,d,e,f,g,dp;
reg [7:0] seg; //g,f,e,d,c,b,a,dp 
assign ds =0;
assign dp=seg[0];
assign a=seg[1];
assign b=seg[2];
assign c=seg[3];
assign d=seg[4];
assign e=seg[5];
assign f=seg[6];
assign g=seg[7];
always @(d_in)
     case(d_in)
     4'b0000: seg = 8'b01111110; //g,f,e,d,c,b,a,dp
     4'b0001: seg = 8'b00001100;
     4'b0010: seg = 8'b10110110;
     4'b0011: seg = 8'b10011110;
     4'b0100: seg = 8'b11001100;
     4'b0101: seg = 8'b11011010;
     4'b0110: seg = 8'b11111010;
     4'b0111: seg = 8'b00001110;
     4'b1000: seg = 8'b11111110;
     4'b1001: seg = 8'b11011110;
     4'b1010: seg = 8'b11101110;
     4'b1011: seg = 8'b11111000;
     4'b1100: seg = 8'b01110010;
     4'b1101: seg = 8'b10111100;
     4'b1110: seg = 8'b11110010;
     4'b1111: seg = 8'b11100010;
     endcase

 endmodule