Verilog 练习 7段数码管译码器

 代码如下（testbench代码是我自己写的，仅供参考）

//2021-11-2
//7段码译码器；
`timescale 1ns/10ps
module seg_dec(num,a_g);
input[3:0] num;
output[6:0] a_g;  //a_g[6:0]-->{a,b,c,d,e,f,g};

reg[6:0] a_g;
always@(num) begin
	case(num)
	4'd0: a_g<=7'b111_1110;
	4'd1: a_g<=7'b011_0000;
	4'd2: a_g<=7'b110_1101;
	4'd3: a_g<=7'b111_1100;
	4'd4: a_g<=7'b011_0011;
	4'd5: a_g<=7'b101_1011;
	4'd6: a_g<=7'b101_1111;
	4'd7: a_g<=7'b111_0000;
	4'd8: a_g<=7'b111_1111;
	4'd9: a_g<=7'b111_1011;
	default: a_g<=7'b000_0001;
	endcase
end

endmodule

//----testbench of seg_dec----
module seg_dec_tb;
reg[3:0] num_in;
wire[7:0] a_g_out;

seg_dec seg_dec(.num(num_in),.a_g(a_g_out));

initial begin
	num_in=0;
	#140 $stop;
end 
 
always#10 num_in<=num_in+1;

endmodule

仿真结果如下

 https://www.bilibili.com/video/BV1hX4y137Ph?p=3&spm_id_from=pageDriver