扩展型74HC4511 verilog代码

m0_54195931

已于 2022-04-28 21:08:35 修改

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文章标签： HC4511 显示模块数字输入逻辑控制编码转换

于 2022-04-28 14:52:55 首次发布

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版权

module HC4511(A,Seg,LT_N,BI_N,LE);
    input LT_N,BI_N,LE;
    input [3:0]A;
    output [7:0]Seg;
    reg [7:0]Seg;
always@(A or LT_N or BI_N or LE)
    begin
        if(!LT_N)   Seg = 8'b11111111;
        else if(!BI_N)  Seg = 8'b00000000;
        else if(LE)   Seg = Seg;
        else
            case(A)
                4'd0:Seg = 8'b00111111;
                4'd1:Seg = 8'b00000110;
                4'd2:Seg = 8'b01011011;
                4'd3:Seg = 8'b01001111;
                4'd4:Seg = 8'b01100110;
                4'd5:Seg = 8'b01101101;
                4'd6:Seg = 8'b01111101;
                4'd7:Seg = 8'b00000111;
                4'd8:Seg = 8'b01111111;
                4'd9:Seg = 8'b01101111;
                4'ha:Seg = 8'b01110111;
                4'hb:Seg = 8'b01111100;
                4'hc:Seg = 8'b00111001;
                4'hd:Seg = 8'b01011110;
                4'he:Seg = 8'b01111001;
                4'hf:Seg = 8'b01110001;
                default:;
            endcase
    end
endmodule

可实现超过9的数据显示