VHDL——描述电路

1.逻辑电路

2.真值表

3.VHDL语言

library ieee;
use ieee.std_logic_1164.all;

entity discribe is
    port(a,b,c : in boolean;
	      y : out boolean);
end discribe;

architecture logc of discribe is
begin
    process(a,b,c)
	 variable ot : boolean;
	 begin
	     if a then 
		   ot := b;
		  else
		   ot := c;
		  end if;
	 y <= ot;
	 end process;
end logc;