寄存器模块设计
寄存器模块验证
计时模块设计
计时模块验证
七段显示模块和顶层模块设计
七段显示模块验证
package display_pkg;
import uvm_pkg::*;
`include "uvm_macros.svh"
class dis_trans extends uvm_sequence_item;
rand int time_h;
rand int time_m;
rand int time_s;
rand int time_ms;
constraint scs{
time_h inside {[0:11]};
time_m inside {[0:59]};
time_s inside {[0:59]};
time_ms inside {[0:999]};
};
`uvm_object_utils_begin(dis_trans)
`uvm_field_int(time_h,UVM_ALL_ON)
`uvm_field_int(time_m,UVM_ALL_ON)
`uvm_field_int(time_s,UVM_ALL_ON)
`uvm_field_int(time_ms,UVM_ALL_ON)
`uvm_object_utils_end
function new (string name = "dis_trans");
super.new(name);
endfunction
endclass
class dis_coverage extends uvm_component;
local virtual dis_inter intf;
`uvm_component_utils(dis_coverage)
covergroup dis_cover;
hour:coverpoint intf.h {
type_option.weight = 0;
bins hi = {[21:23]};
bins mid = {[3:20]};
bins lo = {0,1};
}
min:coverpoint intf.m{
type_option.weight = 0;
bins hi = {[55:59]};
bins mid_h = {[30:54]};
bins mid_l = {[6:29]};
bins lo = {[0:5]};
}
sec:coverpoint intf.s{
type_option.weight = 0;
bins hi = {[55:59]};
bins mid_h = {[30:54]};
bins mid_l = {[6:29]};
bins lo = {[0:5]};
}
cross_group :cross hour, min, sec{
bins hour_hi = binsof (hour.hi);
bins hour_mid = binsof (hour.mid);
bins hour_lo = binsof (hour.lo);
bins min_hi = binsof (min.hi);
bins min_mid_h = binsof (min.mid_h);
bins min_mid_l = binsof (min.mid_l);
bins min_lo = binsof (min.lo);
bins sec_hi = binsof (sec.hi);
bins sec_mid_h = binsof (sec.mid_h);
bins sec_mid_l = binsof (sec.mid_l);
bins sec_lo = binsof (sec.lo);
bins hour_min_sec_hhh = binsof (hour.hi) && binsof (min.hi) && binsof (sec.hi);
bins hour_min_sec_hhm_h = binsof (hour.hi) && binsof (min.hi) && binsof (sec.mid_h);
bins hour_min_sec_hhm_l = binsof (hour.hi) && binsof (min.hi) && binsof (sec.mid_l);
bins hour_min_sec_hhl = binsof (hour.hi) && binsof (min.hi) && binsof (sec.lo);
bins hour_min_sec_hm_hh = binsof (hour.hi) && binsof (min.mid_h) && binsof (sec.hi);
bins hour_min_sec_hm_hm_h = binsof (hour.hi) && binsof (min.mid_h) && binsof (sec.mid_h);
bins hour_min_sec_hm_hm_l = binsof (hour.hi) && binsof (min.mid_h) && binsof (sec.mid_l);
bins hour_min_sec_hm_hl = binsof (hour.hi) && binsof (min.mid_h) && binsof (sec.lo);
bins hour_min_sec_hm_lh = binsof (hour.hi) && binsof (min.mid_l) && binsof (sec.hi);
bins hour_min_sec_hm_lm_h = binsof (hour.hi) && binsof (min.mid_l) && binsof (sec.mid_h);
bins hour_min_sec_hm_lm_l = binsof (hour.hi) && binsof (min.mid_l) && binsof (sec.mid_l);
bins hour_min_sec_hm_ll = binsof (hour.hi) && binsof (min.mid_l) && binsof (sec.lo);
bins hour_min_sec_hlh = binsof (hour.hi) && binsof (min.lo) && binsof (sec.hi);
bins hour_min_sec_hlm_h = binsof (hour.hi) && binsof (min.lo) && binsof (sec.mid_h);
bins hour_min_sec_hlm_l = binsof (hour.hi) && binsof (min.lo) && binsof (sec.mid_l);
bins hour_min_sec_hll = binsof (hour.hi) && binsof (min.lo) && binsof (sec.lo);
bins hour_min_sec_mhh = binsof (hour.mid) && binsof (min.hi) && binsof (sec.hi);
bins hour_min_sec_mhm_h = binsof (hour.mid) && binsof (min.hi) && binsof (sec.mid_h);
bins hour_min_sec_mhm_l = binsof (hour.mid) && binsof (min.hi) && binsof (sec.mid_l);
bins hour_min_sec_mhl = binsof (hour.mid) && binsof (min.hi) && binsof (sec.lo);
bins hour_min_sec_mm_hh = binsof (hour.mid) && binsof (min.mid_h) && binsof (sec.hi);
bins hour_min_sec_mm_hm_h = binsof (hour.mid) && binsof (min.mid_h) && binsof (sec.mid_h);
bins hour_min_sec_mm_hm_l = binsof (hour.mid) && binsof (min.mid_h) && binsof (sec.mid_l);
bins hour_min_sec_mm_hl = binsof (hour.mid) && binsof (min.mid_h) && binsof (sec.lo);
bins hour_min_sec_mm_lh = binsof (hour.mid) && binsof (min.mid_l) && binsof (sec.hi);
bins hour_min_sec_mm_lm_h = binsof (hour.mid) && binsof (min.mid_l) && binsof (sec.mid_h);
bins hour_min_sec_mm_lm_l = binsof (hour.mid) && binsof (min.mid_l) && binsof (sec.mid_l);
bins hour_min_sec_mm_ll = binsof (hour.mid) && binsof (min.mid_l) && binsof (sec.lo);
bins hour_min_sec_mlh = binsof (hour.mid) && binsof (min.lo) && binsof (sec.hi);
bins hour_min_sec_mlm_h = binsof (hour.mid) && binsof (min.lo) && binsof (sec.mid_h);
bins hour_min_sec_mlm_l = binsof (hour.mid) && binsof (min.lo) && binsof (sec.mid_l);
bins hour_min_sec_mll = binsof (hour.mid) && binsof (min.lo) && binsof (sec.lo);
bins hour_min_sec_lhh = binsof (hour.lo) && binsof (min.hi) && binsof (sec.hi);
bins hour_min_sec_lhm_h = binsof (hour.lo) && binsof (min.hi) && binsof (sec.mid_h);
bins hour_min_sec_lhm_l = binsof (hour.lo) && binsof (min.hi) && binsof (sec.mid_l);
bins hour_min_sec_lhl = binsof (hour.lo) && binsof (min.hi) && binsof (sec.lo);
bins hour_min_sec_lm_hh = binsof (hour.lo) && binsof (min.mid_h) && binsof (sec.hi);
bins hour_min_sec_lm_hm_h = binsof (hour.lo) && binsof (min.mid_h) && binsof (sec.mid_h);
bins hour_min_sec_lm_hm_l = binsof (hour.lo) && binsof (min.mid_h) && binsof (sec.mid_l);
bins hour_min_sec_lm_hl = binsof (hour.lo) && binsof (min.mid_h) && binsof (sec.lo);
bins hour_min_sec_lm_lh = binsof (hour.lo) && binsof (min.mid_l) && binsof (sec.hi);
bins hour_min_sec_lm_lm_h = binsof (hour.lo) && binsof (min.mid_l) && binsof (sec.mid_h);
bins hour_min_sec_lm_lm_l = binsof (hour.lo) && binsof (min.mid_l) && binsof (sec.mid_l);
bins hour_min_sec_lm_ll = binsof (hour.lo) && binsof (min.mid_l) && binsof (sec.lo);
bins hour_min_sec_llh = binsof (hour.lo) && binsof (min.lo) && binsof (sec.hi);
bins hour_min_sec_llm_h = binsof (hour.lo) && binsof (min.lo) && binsof (sec.mid_h);
bins hour_min_sec_llm_l = binsof (hour.lo) && binsof (min.lo) && binsof (sec.mid_l);
bins hour_min_sec_lll = binsof (hour.lo) && binsof (min.lo) && binsof (sec.lo);
}
endgroup
function new(string name = "dis_coverage", uvm_component parent);
super.new(name,parent);
dis_cover = new();
endfunction
task run_phase (uvm_phase phase);
forever begin
@(posedge intf.clk);
this.dis_cover.sample();
end
endtask
function void set_interface(virtual dis_inter intf);
this.intf = intf;
endfunction
endclass
class dis_driver extends uvm_driver #(dis_trans);
local virtual dis_inter intf;
`uvm_component_utils(dis_driver)
function new(string name = "dis_driver", uvm_component parent);
super.new(name,parent);
endfunction
function void set_interface(virtual dis_inter intf);
this.intf = intf;
endfunction
task run_phase(uvm_phase phase);
fork
this.do_driver();
// this.do_reset();
join
endtask
task do_driver();
dis_trans req,rsp;
@(posedge intf.rstn);
forever begin
seq_item_port.get_next_item(req);
this.do_write(req);
void'($cast(rsp,req.clone()));
rsp.set_sequence_id(req.get_sequence_id());
seq_item_port.item_done(rsp);
end
endtask
task do_write(input dis_trans t);
repeat (3) @(posedge intf.clk);
intf.h <= t.time_h;
intf.m <= t.time_m;
intf.s <= t.time_s;
endtask
// task do_reset();
// @(negedge intf.rstn)
// intf.h = 0;
// intf.m = 0;
// intf.s = 0;
// intf.ms = 0;
// endtask
endclass
class dis_sequencer extends uvm_sequencer #(dis_trans);
`uvm_component_utils(dis_sequencer)
function new(string name = "dis_sequencer", uvm_component parent);
super.new(name,parent);
endfunction
endclass
class dis_sequence extends uvm_sequence#(dis_trans);
local virtual dis_inter intf;
`uvm_object_utils(dis_sequence)
function new(string name = "dis_sequence");
super.new(name);
endfunction
task body();
repeat (1111) do_gen();
endtask
task do_gen();
dis_trans req,rsp;
`uvm_do(req)
get_response(rsp);
endtask
endclass
class dis_monitor extends uvm_monitor;
local virtual dis_inter intf;
`uvm_component_utils(dis_monitor)
function new(string name = "dis_monitor", uvm_component parent);
super.new(name, parent);
endfunction
function void set_interface (virtual dis_inter intf);
this.intf = intf;
endfunction
endclass
class dis_agent extends uvm_agent;
dis_sequencer sequencer;
dis_monitor monitor;
dis_driver driver;
dis_coverage coverage;
local virtual dis_inter intf;
`uvm_component_utils(dis_agent)
function new (string name = "dis_agent", uvm_component parent);
super.new(name,parent);
endfunction
function void build_phase (uvm_phase phase);
super.build_phase(phase);
driver = dis_driver::type_id::create("driver",this);
monitor = dis_monitor::type_id::create("monitor",this);
sequencer = dis_sequencer::type_id::create("sequencer",this);
coverage = dis_coverage::type_id::create("coverage",this);
endfunction
function void connect_phase (uvm_phase phase);
super.connect_phase(phase);
driver.seq_item_port.connect(sequencer.seq_item_export);
endfunction
function void set_interface(virtual dis_inter intf);
this.intf = intf;
monitor.set_interface(intf);
driver.set_interface(intf);
coverage.set_interface(intf);
endfunction
endclass
class dis_test extends uvm_test;
dis_agent agent;
virtual dis_inter intf;
`uvm_component_utils(dis_test)
function new(string name = "dis_test", uvm_component parent);
super.new(name,parent);
endfunction
function void build_phase (uvm_phase phase);
super.build_phase(phase);
agent = dis_agent::type_id::create("agent",this);
if(!uvm_config_db#(virtual dis_inter)::get(this,"","intf",intf)) begin
`uvm_info("INTF","cannot get the handle of interface",UVM_LOW)
end
endfunction
function void connect_phase (uvm_phase phase);
super.connect_phase(phase);
this.set_interface(intf);
endfunction
function void set_interface(virtual dis_inter intf);
this.intf = intf;
agent.set_interface(intf);
endfunction
task run_phase(uvm_phase phase);
dis_sequence t;
phase.raise_objection(this);
t = new("t");
t.start(agent.sequencer);
phase.drop_objection(this);
endtask
endclass
endpackage
顶层模块验证
验证环境代码
利用virtual_sequencer和virtual_sequence连接各个模块sequencer和sequence并例化在clock_env，并封装在顶层clock_gen_test测试模块中。将各个模块中monitor中数据利用TLM_fifo传入顶层scoreboard中与reference model输出数据进行比较。
package clock_pkg;
import uvm_pkg::*;
`include "uvm_macros.svh"
`include "parameter_clock.v"
import display_pkg::*;
import reg_pkg::*;
typedef struct packed{
bit [7:0] h;
bit [7:0] m;
bit [7:0] s;
bit [9:0] ms;} dis_mon;
class clock_refmodel extends uvm_component;
mailbox #(reg_trans) reg_mb;
uvm_blocking_get_port #(reg_trans) reg_bg_port;
uvm_tlm_fifo #(dis_mon) dis_bg_fifo;
virtual reg_inter reg_intf;
`uvm_component_utils(clock_refmodel)
function new (string name = "clock_refmodel", uvm_component parent);
super.new(name,parent);
endfunction
function void build_phase(uvm_phase phase);
dis_bg_fifo = new("dis_bg_fifo", this);
reg_bg_port = new("reg_bg_port", this);
reg_mb = new();
endfunction
function void set_interface(virtual reg_inter reg_intf);
this.reg_intf = reg_intf;
endfunction
task run_phase(uvm_phase phase);
fork
do_reg_mon();
do_gen_clock();
join
endtask
task do_reg_mon();
reg_trans t;
forever begin
reg_bg_port.get(t);
reg_mb.put(t);
end
endtask
task do_gen_clock;
reg_trans t;
dis_mon m;
forever begin
repeat (150) @(posedge reg_intf.clk);
reg_mb.get(t);
t.print();
if (t.flag == 1) begin
if (t.up == 1) begin
m.h = m.h + 1;
if (m.h == 24) begin
m.h = 0;
end
end
else if (t.dn == 1) begin
m.h = m.h - 1;
if (m.h == 8'hff) begin
m.h = 23;
end
end
end
if (t.flag == 2) begin
if (t.up == 1) begin
m.m = m.m + 1;
if (m.m == 60) begin
m.m = 0;
end
end
else if (t.dn == 1) begin
m.m = m.m - 1;
if (m.m == 8'hff) begin
m.m = 59;
end
end
end
if (t.flag == 3) begin
if (t.up == 1) begin
m.s = m.s + 1;
if (m.s == 60) begin
m.s = 0;
end
end
else if (t.dn == 1) begin
m.s = m.s - 1;
if (m.s == 8'hff) begin
m.s = 59;
end
end
end
if (t.flag == 0)begin
repeat(3) ms_gen(m);
end
dis_bg_fifo.put(m);
`uvm_info("REF_MON",$sformatf("time %32d, n.h %32d", $time,m.h) ,UVM_LOW)
`uvm_info("REF_MON",$sformatf("time %32d, n.m %32d", $time,m.m) ,UVM_LOW)
`uvm_info("REF_MON",$sformatf("time %32d, n.s %32d", $time,m.s) ,UVM_LOW)
`uvm_info("REF_MON",$sformatf("time %32d, n.ms %32d", $time,m.ms) ,UVM_LOW)
end
endtask
task ms_gen(inout dis_mon m);
m.ms = m.ms + 1'b1;
if (m.ms == 10'b11111_01001) begin
m.s = m.s + 1'b1;
m.ms = 10'd0;
end
if (m.s == 8'd60) begin
m.m = m.m + 1'b1;
m.s = 8'd0;
end
if (m.m == 8'd60) begin
m.h = m.h + 1'b1;
m.m = 8'd0;
end
if (m.h == 8'd24) begin
m.h = 8'd0;
end
endtask
endclass
class clock_checker extends uvm_scoreboard;
int count;
int error;
virtual dis_inter dis_intf;
uvm_blocking_get_port #(dis_mon) dis_bg_port;
`uvm_component_utils(clock_checker)
function new (string name = "clock_checker", uvm_component parent);
super.new(name,parent);
endfunction
function void set_interface (virtual dis_inter dis_intf);
this.dis_intf = dis_intf;
endfunction
function void build_phase(uvm_phase phase);
super.build_phase(phase);
dis_bg_port = new("dis_bg_port",this);
endfunction
task run_phase(uvm_phase phase);
forever begin
do_clock_compare();
end
endtask
task do_clock_compare();
dis_mon m,n;
dis_bg_port.get(n);
m.h = dis_intf.h;
m.m = dis_intf.m;
m.s = dis_intf.s;
`uvm_info("DIS_MON",$sformatf("time %32d, m.h %32d", $time,m.h) ,UVM_LOW)
`uvm_info("DIS_MON",$sformatf("time %32d, m.m %32d", $time,m.m) ,UVM_LOW)
`uvm_info("DIS_MON",$sformatf("time %32d, m.s %32d", $time,m.s) ,UVM_LOW)
if (m.h == n.h && m.m == n.m && m.s == n.s) begin
count ++;
end
else begin
error ++;
count ++;
end
`uvm_info("ERROR",$sformatf("error times %32d", error) ,UVM_LOW)
`uvm_info("COUNT",$sformatf("count times %32d", count) ,UVM_LOW)
endtask
endclass
class clock_coverage extends uvm_component;
local virtual dis_inter dis_intf;
`uvm_component_utils(clock_coverage)
covergroup clock_cover;
hour_l:coverpoint dis_intf.toh[7:0]{
// type_option.weight = 0;
bins h_0 = {8'h3f};
bins h_1 = {8'h06};
bins h_2 = {8'h5b};
bins h_3 = {8'h4f};
bins h_4 = {8'h66};
bins h_5 = {8'h6d};
bins h_6 = {8'h7d};
bins h_7 = {8'h27};
bins h_8 = {8'h7f};
bins h_9 = {8'h6f};
}
hour_h:coverpoint dis_intf.toh[15:8]{
// type_option.weight = 0;
bins h_1 = {8'h06};
bins h_0 = {8'h3f};
bins h_2 = {8'h5b};
}
mins_l:coverpoint dis_intf.tom[7:0]{
// type_option.weight = 0;
bins m_0 = {8'h3f};
bins m_1 = {8'h06};
bins m_2 = {8'h5b};
bins m_3 = {8'h4f};
bins m_4 = {8'h66};
bins m_5 = {8'h6d};
bins m_6 = {8'h7d};
bins m_7 = {8'h27};
bins m_8 = {8'h7f};
bins m_9 = {8'h6f};
}
mins_h:coverpoint dis_intf.tom[15:8]{
// type_option.weight = 0;
bins m_0 = {8'h3f};
bins m_1 = {8'h06};
bins m_2 = {8'h5b};
bins m_3 = {8'h4f};
bins m_4 = {8'h66};
bins m_5 = {8'h6d};
}
sec_l:coverpoint dis_intf.tos[7:0]{
// type_option.weight = 0;
bins s_0 = {8'h3f};
bins s_1 = {8'h06};
bins s_2 = {8'h5b};
bins s_3 = {8'h4f};
bins s_4 = {8'h66};
bins s_5 = {8'h6d};
bins s_6 = {8'h7d};
bins s_7 = {8'h27};
bins s_8 = {8'h7f};
bins s_9 = {8'h6f};
}
sec_h:coverpoint dis_intf.tos[15:8]{
// type_option.weight = 0;
bins s_0 = {8'h3f};
bins s_1 = {8'h06};
bins s_2 = {8'h5b};
bins s_3 = {8'h4f};
bins s_4 = {8'h66};
bins s_5 = {8'h6d};
}
cross_group_h: cross hour_l, hour_h{
bins h_0x = binsof (hour_h.h_0) && binsof (hour_l);
bins h_1x = binsof (hour_h.h_1) && binsof (hour_l);
bins h_2x = binsof (hour_h.h_2) && binsof (hour_l);
}
cross_group_m: cross mins_l, mins_h{
bins m_0x = binsof (mins_h.m_0) && binsof (mins_l);
bins m_1x = binsof (mins_h.m_1) && binsof (mins_l);
bins m_2x = binsof (mins_h.m_2) && binsof (mins_l);
bins m_3x = binsof (mins_h.m_3) && binsof (mins_l);
bins m_4x = binsof (mins_h.m_4) && binsof (mins_l);
bins m_5x = binsof (mins_h.m_5) && binsof (mins_l);
}
cross_group_s: cross sec_l, sec_h{
bins s_0x = binsof (sec_h.s_0) && binsof (sec_l);
bins s_1x = binsof (sec_h.s_1) && binsof (sec_l);
bins s_2x = binsof (sec_h.s_2) && binsof (sec_l);
bins s_3x = binsof (sec_h.s_3) && binsof (sec_l);
bins s_4x = binsof (sec_h.s_4) && binsof (sec_l);
bins s_5x = binsof (sec_h.s_5) && binsof (sec_l);
}
endgroup
function new(string name = "clock_coverage", uvm_component parent);
super.new(name,parent);
clock_cover = new();
endfunction
function void set_interface(virtual dis_inter dis_intf);
this.dis_intf = dis_intf;
endfunction
task run_phase (uvm_phase phase);
forever begin
@(posedge dis_intf.clk);
this.clock_cover.sample();
end
endtask
endclass
class clock_virtual_sequencer extends uvm_sequencer;
dis_sequencer dis_sqr;
reg_sequencer reg_sqr;
`uvm_component_utils(clock_virtual_sequencer)
function new (string name = "clock_virtual_sequencer", uvm_component parent);
super.new(name,parent);
endfunction
endclass
class clock_env extends uvm_env;
reg_agent reg_agt;
dis_agent dis_agt;
clock_refmodel refmod;
clock_checker cher;
clock_coverage coverage;
clock_virtual_sequencer vir_sqr;
`uvm_component_utils(clock_env)
function new (string name = "clock_env", uvm_component parent);
super.new(name,parent);
endfunction
function void build_phase (uvm_phase phase);
super.build_phase(phase);
reg_agt = reg_agent::type_id::create("reg_agt",this);
dis_agt = dis_agent::type_id::create("dis_agt",this);
vir_sqr = clock_virtual_sequencer::type_id::create("vir_sqr",this);
refmod = clock_refmodel::type_id::create("refmod",this);
cher = clock_checker::type_id::create("cher",this);
coverage = clock_coverage::type_id::create("coverage",this);
endfunction
function void connect_phase(uvm_phase phase);
super.connect_phase(phase);
vir_sqr.dis_sqr = dis_agt.sequencer;
vir_sqr.reg_sqr = reg_agt.sequencer;
refmod.reg_bg_port.connect(reg_agt.monitor.reg_bg_fifo.blocking_get_export);
cher.dis_bg_port.connect(refmod.dis_bg_fifo.blocking_get_export);
// cher.dis_bgf_port.connect(dis_agt.monitor.dis_tlmf_fifo.blocking_get_export);
// cher.dis_bgl_port.connect(dis_agt.monitor.dis_tlml_fifo.blocking_get_export);
endfunction
endclass
class clock_virtual_base_sequence extends uvm_sequence;
dis_sequence dis_seq;
reg_sequence reg_seq;
`uvm_object_utils(clock_virtual_base_sequence)
`uvm_declare_p_sequencer(clock_virtual_sequencer)
function new (string name = "clock_virtual_base_sequence");
super.new(name);
endfunction
virtual task body();
this.do_reg();
this.do_dis();
endtask
virtual task do_reg();
endtask
virtual task do_dis();
endtask
endclass
class clock_base_test extends uvm_test;
local virtual dis_inter dis_intf;
local virtual reg_inter reg_intf;
// virtual clock_inter clock_intf;
clock_env env;
`uvm_component_utils(clock_base_test)
function new(string name = "clock_base_test", uvm_component parent);
super.new(name,parent);
endfunction
function void build_phase (uvm_phase phase);
super.build_phase(phase);
if (uvm_config_db#(virtual reg_inter)::get(this,"","reg_intf",reg_intf)) begin
`uvm_info("REG_INTF"," get handle of reg_interface", UVM_LOW)
end
if (uvm_config_db#(virtual dis_inter)::get(this,"","dis_intf",dis_intf)) begin
`uvm_info("DIS_INTF"," get handle of dis_interface", UVM_LOW)
end
// if (!uvm_config_db#(virtual clock_inter)::get(this,"","clock_intf",clock_intf)) begin
// `uvm_info("CLOCK_INTF","cannot get handle of clock_interface", UVM_LOW)
// end
this.env = clock_env::type_id::create("env",this);
endfunction
function void connect_phase(uvm_phase phase);
super.connect_phase(phase);
this.set_interface(dis_intf,reg_intf);
endfunction
virtual function void set_interface(virtual dis_inter dis_intf,
virtual reg_inter reg_intf
);
if(reg_intf == null) $error("mcdf interface handle is NULL");
else begin
this.reg_intf = reg_intf;
this.env.reg_agt.set_interface(reg_intf);
`uvm_info("SET_INTREFACE"," get handle of reg_interface", UVM_LOW)
end
this.dis_intf = dis_intf;
this.env.dis_agt.set_interface(dis_intf);
`uvm_info("SET_INTERFACE"," get handle of reg_interface", UVM_LOW)
this.env.coverage.set_interface(dis_intf);
this.env.cher.set_interface(dis_intf);
this.env.refmod.set_interface(reg_intf);
endfunction
task run_phase (uvm_phase phase);
phase.raise_objection(this);
this.do_top_virtual_sequence();
phase.drop_objection(this);
endtask
virtual task do_top_virtual_sequence();
endtask
endclass
class clock_virtual_test_sequence extends clock_virtual_base_sequence;
`uvm_object_utils(clock_virtual_test_sequence)
function new(string name = "clock_virtual_test_sequence");
super.new(name);
endfunction
task do_reg();
`uvm_do_on(reg_seq,p_sequencer.reg_sqr)
endtask
endclass
class clock_gen_test extends clock_base_test;
`uvm_component_utils(clock_gen_test)
function new(string name = "clock_gen_test", uvm_component parent);
super.new(name,parent);
endfunction
task do_top_virtual_sequence();
clock_virtual_test_sequence seq = new("seq");
seq.start(env.vir_sqr);
endtask
endclass
endpackage
**顶层配置**
```csharp
```csharp
```csharp
```cpp
```php
```csharp
```csharp
`timescale 1ns/1ps
`include "parameter_clock.v"
interface clock_inter(input clk, input rstn);
endinterface
interface reg_inter (input clk, input rstn);
logic [7:0] reg_i;
logic [31:0] reg_out;
logic [1:0] flag;
logic dn;
logic up;
clocking reg_cb @(posedge clk);
default input #1step output #1ns;
input flag,dn,up,reg_out;
output reg_i;
endclocking
endinterface
interface dis_inter (input clk,input rstn);
logic [7:0] h;
logic [7:0] m;
logic [7:0] s;
logic [15:0]toh;
logic [15:0]tom;
logic [15:0]tos;
clocking dis_cb @(posedge clk);
default input #1ns output #1ns;
input toh,tom,tos;
endclocking
endinterface
module tb();
logic clk;
logic rstn;
clock dut(
.clk_i (clk)
,.rstn_i (rstn)
,.cmd_out (reg_intf.reg_out)
,.reg_i (reg_intf.reg_i)
,.h_dis (dis_intf.toh)
,.m_dis (dis_intf.tom)
,.s_dis (dis_intf.tos)
);
initial begin
clk <= 0;
forever begin
#5 clk <= ~clk;
end
end
initial begin
#5 rstn <= 0;
repeat (10) @(posedge clk);
rstn <= 1;
end
import uvm_pkg::*;
`include "uvm_macros.svh"
import reg_pkg::*;
import display_pkg::*;
import clock_pkg::*;
reg_inter reg_intf(.*);
dis_inter dis_intf(.*);
clock_inter clock_intf(.*);
assign dis_intf.h = tb.dut.dis.h;
assign dis_intf.m = tb.dut.dis.m;
assign dis_intf.s = tb.dut.dis.s;
initial begin
uvm_config_db#(virtual reg_inter)::set(uvm_root::get(),"uvm_test_top","reg_intf",reg_intf);
uvm_config_db#(virtual dis_inter)::set(uvm_root::get(),"uvm_test_top","dis_intf",dis_intf);
uvm_config_db#(virtual clock_inter)::set(uvm_root::get(),"uvm_test_top","clock_intf",clock_intf);
run_test("clock_gen_test");
end
endmodule
电子表仿真结果
功能覆盖率
scorebored比较结果
refmodel数据与scorebored比较结果
扫一扫
248
被折叠的 条评论
为什么被折叠?
到【灌水乐园】发言
