电子表设计与验证（时钟频率选择模块验证）

最新推荐文章于 2023-04-11 10:56:44 发布

王亮小亮

最新推荐文章于 2023-04-11 10:56:44 发布

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分类专栏：笔记文章标签： verilog systemverilog

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电子表设计与验证（时钟频率选择模块验证）

利用UVM搭建简单验证平台

package div_pkg;
import uvm_pkg::*;
`include "uvm_macros.svh"
 
class div_trans extends uvm_sequence_item;

rand int  div_n;
rand int  clk_out;
constraint divc{
   
                div_n inside {
   [10:50]};
               };

 `uvm_object_utils_begin(div_trans)
  `uvm_field_int(div_n,UVM_ALL_ON)
  `uvm_field_int(clk_out,UVM_ALL_ON)
 `uvm_object_utils_end
 
 function new(string name = "div_trans");
   super.new(name);
 endfunction
endclass

class div_driver extends uvm_driver #(div_trans);
  virtual div_inter intf;
 `uvm_component_utils(div_driver)

  function new(string name = "div_driver", uvm_component parent);
   super.new(name,parent);
  endfunction

  function void set_interface(virtual div_inter intf);
    this.intf = intf;
  endfunction

  task run_phase (uvm_phase phase);
    super.run_phase(phase);
    fork    
     this.do_driver();
     this.do_reset();
    join
  endtask

  task do_driver();
    div_trans req,rsp;
    forever begin
       repeat (100) @(posedge intf.clk)
       seq_item_port.get_next_item(req);
       this.write(req);
       void'($cast(rsp,req.clone()));
       rsp.set_sequence_id(req.get_sequence_id(