学习十八-UJA107xA简介及移植2

目录

8、移植代码

9、实验

10、SPI库函数

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8、移植代码

8.1 UJA107xA_reg.h

        直接将NXP_SBC_UJA107xA.h内容全部复制过来。

/*
 * UJA107xA_reg.h
 *
 *  Created on: 2021年7月18日
 *      Author:
 */

#ifndef __UJA107XA_REG_H_
#define __UJA107XA_REG_H_



/// Configures header file for the existing UJA107xA family member, e.g. UJA1078A
/// Must be copied to the global project definitions
#define UJA1078A

#define NoInterruptPending 0x7000 /* 0111 000000000000 */
#define DeviceIdPattern 0x4308    /* 0100 0011 0000 1000 */
#define UJA1078A_DeviceIdPattern 0x4308  /* */
#define UJA1075A_DeviceIdPattern 0x4208  /* */
#define UJA1076A_DeviceIdPattern 0x4008  /* */
#define UJA1079A_DeviceIdPattern 0x4200  /* */


/// Watchdog and Status Register address
#define WDSR_ADDRESS_MASK 0x0000
/// Watchdog and Status Register read mask
#define WDSR_READ_MASK 0x1000 /* 0001 0000 0000 0000 */
/// Watchdog and Status Register write mask
#define WDSR_WRITE_MASK 0xEFFF /* 1110 1111 1111 1111 */
/// Watchdog Mode Control
#define WDSR_WMC_MASK 0x0800 /* */
/// Nominal Watchdog Period
#define WDSR_NWP_MASK 0x0700 /* */
/// Watchdog Off Status
#define WDSR_WOS_MASK 0x0080 /* */
///  Software Reset
#define WDSR_SWR_MASK 0x0080 /* 0000 0000 1000 0000*/
///  V1 Status
#define WDSR_V1S_MASK 0x0040 /* */

#ifndef UJA1079A
/// V2 Status; not available for UJA1079A
#define WDSR_V2S_MASK 0x0020 /* 0000 0000 0010 0000 */
#endif

/// Wake-Up Status 1
#define WDSR_WLS1_MASK 0x0010 /* */
/// Wake-Up Status 2
#define WDSR_WLS2_MASK 0x0008 /* */



/// Mode Control Register address
#define MCR_ADDRESS_MASK 0x2000 /* */
/// Mode Control Register read mask
#define MCR_READ_MASK 0x3000 /* */
/// Mode Control Register write mask
#define MCR_WRITE_MASK 0xEFFF /* */
/// Mode Control
#define MCR_MC_MASK 0x0c00 /* */
/// Mode Control mask for Normal Mode with disabled V2 (MC = 2)
#define MCR_MC2_MASK 0x0800 /* */
/// Mode Control mask for Normal Mode with enabled V2 (MC = 3)
#define MCR_MC3_MASK 0x0c00 /* 0000 1100 0000 0000 */
/// Mode Control mask for Sleep Mode (MC = 1)
#define MCR_MC1_MASK 0x0400 /* */
/// Limp Home Warning Control
#define MCR_LHWC_MASK 0x0200 /* */
/// Limp Home Control
#define MCR_LHC_MASK 0x0100 /* */
/// Enable Control
#define MCR_ENC_MASK 0x0080 /* */

#ifndef UJA1076A
/// LIN Slope Control; not available for UJA1076A
#define MCR_LSC_MASK 0x0040 /* */
#endif

/// Wake Bias Control
#define MCR_WBC_MASK 0x0020 /* */
/// Power Distribution Control
#define MCR_PDC_MASK 0x0010 /* */



/// Interrupt Control Register address
#define ICR_ADDRESS_MASK 0x4000 /* */
/// Interrupt Control Register read mask
#define ICR_READ_MASK 0x5000 /* */
/// Interrupt Control Register write m