verliog学习（3）--同步与异步FIFO编写

验证四要素：

1.灌激励：产生输入信号

2.做预期：产生预期结果

3.集响应：收集输出信号

4.做比较：比较结果

1.设计实现一个16X8的双端口RAM

1.1RAM宽度8bit

1.2RAM深度16

1.3ADDR位宽2^4,取值范围0~15

RAM

(MSB)7           0(ADDR)	6	5	4	3	2	1	0(LSB)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

---

2.verliog代码实现

module  dp_ram(  // port  signal list
      write_clock,
      read_clock,
      write_allow,
      read_allow,
      write_addr,
      read_addr,
      write_data,
      read_data
      );
   

      parameter  DLY  = 1;
      parameter  RAM_WIDTH = 8;
      parameter  RAM_DEPTH = 16;
      parameter  ADDR_WIDTH = 4;

      input       write_clock;
      input       read_clock;
      input       write_allow;
      input       read_allow;
      input  [ADDR_WIDTH - 1:0] write_addr;
      input  [ADDR_WIDTH - 1:0] read_addr;
      input  [RAM_WIDTH - 1:0 ] write_data;
      output [RAM_WIDTH - 1:0 ] read_data;
      reg    [RAM_WIDTH - 1:0 ] read_data;
      reg    [RAM_WIDTH - 1:0 ] memory[RAM_DEPTH-1:0];

 
     // look  at the rising edge of the clock
     always @(posedge write_clock)  begin
        if(write_allow)
             memory[write_addr] <= #DLY write_data;
     end
     
    always @(posedge read_clock)   begin
        if(read_allow)
            read_data <= #DLY memory[read_addr];
    end
endmoudule

3.FIFO原则：满不能写，空不能读

full和empty信号的产生

方法1：用长度计数器factor，执行写操作，factor加1，执行读操作，factor减1。

方法2：地址位扩展1位，用最高位判断空满。

3.1同步FIFO（初始化参数列表）

`timescale 1ns / 10ps
module SYNCFIFO(
      Fifo_rst,   //async reset
      Clock,      //write  and read clock
      Read_enable, //读使能
      Write_enable, //写使能
      Write_data,
      Read_data,
      Full,       //full flag
      Empty,      //empty flag
      Fcounter    //count the number of data in FIFO
     );

  parameter  DATA_WIDTH = 8；
  parameter  ADDR_WIDTH = 9;

  input             Fifo_rst;
  input             Clock;
  input             Read_enable;
  input             Write_enable;
  input [DATA_WIDTH - 1:0] Write_data;
  output  [DATA_WIDTH - 1:0] Read_data;
  output            Full;
  output            Empty;
  output  [ADDR_WIDTH - 1:0] Fcounter;  //总511长度，511组数据
  reg    [DATA_WIDTH - 1:0]  Read_data;  //每组数据8位
  reg               Full; 
  reg               Empty;
  reg    [ADDR_WIDTH - 1:0] Fcounter;
  reg    [ADDR_WIDTH - 1:0] Read_addr;
  reg    [ADDR_WIDTH - 1:0] Write_addr;
  
  wire  Read_allow = (read_enable&&!Empty);  //Empty=1=空，Empty=0=非空
  wire  Write_allow = (write_enable&&!Full)  //Full=1=满，Full=0=没满

3.2同步FIFO(例化)

DUALRAM U_RAM(
         Read_clock(Clock),
         Write_clock(Clock),
         Read_allow(Read_allow),
         Write_allow(Write_allow),
         Read_addr(READ_addr),
         Write_addr(Write_addr),
         Write_data(Write_data),
         Read_data(Read_data)
       );

 always@(posedge Clock or posedge Fifo_rst)
    if (Fifo_rst)
       Empty <= 'b1;
    else
       Empty <= (!Write_enable && (Fcounter[8:1]=8'h0)&&((Fcounter[0] = 0)||Read_enable));

always@(posedge clock or posedge Fifo_rst)
    if(Fifo_rst)
       Full <= 'b0;
    else
       Full <= (!Read_enable && (Fcounter[8:1])=8'hFF)&&((Fcounter[0]==1)||Write_enable));

 
always@(posedge clock or posedge Fifo_rst)
    if(Fifo_rst)
         Read_addr <= 'h0;
    else if(Read_allow)
         Read_addr <= Read_addr + 'b1;
always@(posedge clock or posedge Fifpo_rst)
    if(Fifo_rst)
          Write_addr <= 'h0;
    else if(Write_allow)
          Write_addr <= Write_addr +'b1;

always@(posedge clock or posedge Fifpo_rst)
   if(Fifo_rst)
         Fcounter <= 'h0;
   else if((!Read_allow && Write_allow) ||(Read_allow && !Write_allow)
         if(Write_allow) Fcounter <= Fcounter + 'b1;
         else Fcounter <= - 'b1;
 end